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Accelerating 5G Baseband With Adaptive SoCs

Part 1: New chip architectures for next-gen communication.

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5G new radio (NR) network specifications demand new architectures for radio and access networks. While the 5G NR architecture includes new spectrum and massive MIMO (mMIMO) antennas, corresponding access networks architecture must also evolve to implement the services defined by 5G, which include enhanced Mobile Broadband, Ultra Reliable Low Latency Communications and massive Machine Type Communications. Implementation of these services requires the need for network slicing at different levels of network aggregation nodes. Since software-only solutions are not able to handle increased demand of latency and throughput, this is creating an immense need for acceleration which can be ideally handled by programmable hardware. In this article we specifically discuss the first level of 5G access network aggregation accelerated using adaptive radio-frequency (RF) SoCs.

To handle these new requirements, 3GPP standards organizations have defined different split architectures between 5G radio units (RU) and 5G base stations. The different split architectures play a decisive role in deciding the gNodeB architecture. The higher layer splits define the partition of functionality between the centralized unit (CU) and distributed unit (DU), while the lower layer split defines the functional partition between RU and DU. The lower layer (RU-DU) split is more critical and sensitive in terms of timing and latency and is not standardized.


Figure 1: There are multiple options for lower layer split

While the Split-8 is more common for traditional 4G-LTE networks, Split-7.2 is more commonly adopted for 5G networks. There are multiple variants of option 7.2 split, so it is also referred as option 7-2x as it can move to the left or right, seen in the above figure, based on deployment scenarios. Since the split options are flexible and the interface between the DU and RU is also not rigidly defined in terms of interface protocols, bandwidth, latency, and timing, the programmable processors for interface and functionality implementation at both RU and DU is commonly desired.

Commercially available network interface cards (NICs) can be used to terminate the fronthaul at the DUs of 5G base stations. However, ASIC-based cards can only process the L2-L3 traffic and depend on software for the O-RAN processing, and timing synchronization functionality is not available in most of the general purpose NICs. Since DUs need to have strict timing synchronization with radio units and neighboring base stations, they need to support master, slave, and boundary clock modes of operation from a central GPS clock source. Another important timing functionality is clock holdover circuitry implemented on the base station hardware needed to maintain the clock synchronization in the event of loss of reference clock.

Once the radio IQ data from RU is available for processing, it needs to be processed to be identified as user plane, control plane, management plane, and synchronization plane data in both uplink and downlink direction. The throughput for the synchronization and management plane protocol messages is significantly lower than U-Plane and C-Plane messages, so most of the time synchronization and management messages are handled in the software, with applications running in user space.

3GPP option 7-2 split also defines a clear split between high-PHY and low-PHY functionality where low-PHY functions such as pre-coding, FFT/IFFT and resource element (RE) mapping/de-mapping functions are implemented either on the remote radio unit (RRU), or in fronthaul gateway network node between the RU and DU. The high-PHY functions, which mainly include encode/decode, scrambling and modulation/demodulations, are performed in the DU.


Figure 2: 5G option 7-2 split implementation with Xilinx adaptive RFSoC

The high-PHY functions in gNodeB (DU) can be performed either completely in software or in a combination of software and programmable hardware. The division between software and hardware of high-PHY functions depends on many factors such as:

  • Performance limits of software (or hardware) on overall performance, i.e. software should not put a limit on performance of hardware, and vice versa.
  • Latency considerations: Since 5G specifications put a strong latency requirement on different classes of services, the division should not affect the latency in a negative way.
  • Compatibility with industry standard software APIs: Some of the high-PHY functions have a standard definition of user space APIs so any hardware implementation should maintain the compatibility with standard APIs for seamless transition.

The above criteria outlines the functionality needed for programmable hardware-based accelerators from companies like Xilinx. The ideal accelerator architecture may require implementing complete 5G high-PHY into hardware, which will enable the highest performance and lowest latency while also scaling across multiple mMIMO-based RRU configuration. With the evolving 5G and O-RAN standards and functionality, Xilinx has started with O-RAN processing and lookaside channel encoding/decoding implementation on programmable accelerator cards. Channel coding is one of the high-Phy function, most suitable for programmable hardware because of its compute-intensive nature. It can also be combined with hybrid automatic repeat request (HARQ) functionality to improve performance and lower the latency.

One approach for accelerating 5G L1 High-PHY functionality is based on the adaptable and programmable Xilinx T Series, Telco Accelerator Cards. These cards feature the adaptive RFSoC, which hardens the soft decision based forward error correction (SD-FEC) blocks and also implement HARQ function with on-board DRAM memory for higher and scalable performance. In the next post, we’ll dive into some specifics about Telco Accelerator Cards, while also touching on what’s next for 5G baseband acceleration.



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