Accelerating Chiplets With 112G XSR SerDes PHYs

The fading of Moore’s Law and an almost exponential increase in data is challenging the semiconductor industry as never before. Indeed, zettabytes of data are constantly generated by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. Moreover, sophisticated artificial intelligence (AI) and machine learning (ML) applications are adding new workloads and data streams from the data center to the edge – and driving new architectures to more efficiently process and move data.

To be sure, conventional chip designs are struggling to provide sufficient improvements in power, performance and area (PPA). Moreover, achieving first-time-right silicon has become more difficult with the end of Dennard scaling and slowing of Moore’s Law. Consequently, the industry has adopted chiplet architectures for a number of networking and compute applications. Chip disaggregation, or chiplets, offers a viable alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields.

In this context, the Optical Internetworking Forum (OIF) has outlined the Common Electrical I/O (CEI) 112G XSR (Extra Short Reach) interface. This specification details the interconnect between chiplets, as well as between chiplets and optical engines. The 112G XSR interface offers extremely high throughput capabilities, even though it is designed for low complexity and very low power consumption.

As the semiconductor industry turns towards chiplets to enable high-performance products, chip-to-chip interconnects are “critical” to effectively maintain high speeds and signal integrity across variable physical distances. From our perspective, 112G XSR SerDes PHYs fabricated in advanced process nodes – such as 7nm – can successfully deliver the required speed and signal integrity demanded by chiplets.

112G XSR SerDes PHYs should be tailored for the ultra-low power and area requirements of die-to-die interfaces, supporting PAM-4 signaling with data rates from 72 to 116 Gbps. Moreover, a 112G XSR SerDes PHY should be designed with a system-oriented approach, maximizing flexibility for some of today’s most challenging applications including 112G die-to-die (D2D) interfaces, and 112G die-to-optical engine (D2OE) interfaces.

Additional features should include a high-bandwidth >800Gbps/mm interface, support for channels up to 10dB insertion loss without DFE (to save power), multiple lane configurations to allow flexible ASIC floorplan integration, extensive debug capabilities and interfaces (using an internal microprocessor) and software and scripts for enhanced bring-up and validation.

In conclusion, leveraging the advantages of SoC/ASIC disaggregation is helping the semiconductor industry rapidly evolve on both a micro (silicon) and macro level (data center). With SoC designs fast approaching the outer limits of both yield capabilities and reticle size architecture, the concept of disaggregation has never been timelier.

Learn more about the Rambus 112G XSR SerDes PHY at https://www.rambus.com/interface-ip/serdes/112g-xsr-phy/.

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