Running DRC at each stage as you build your design is a simple, yet obvious way to avoid last-minute surprises.
Applications such as deep-learning, autonomous driving vehicles, and mobility on 5G networks fuel the need for continuous advancements in IC integration. Growing design complexity, pressure on design cycle time, process advancements and increasing verification requirements are driving the need for faster, more efficient physical verification flows. The current state-of-the-art FinFET processes at 7nm and 5nm are complex feats of engineering. As has been the ‘law’ for some time, IC manufacturers can fit more and more transistors into the lithography reticle limit. For example, at 16nm, a typical 80 mm2 die has approximately 2 billion transistors, while at 5nm the same size die has over 12 billion transistors. Foundries utilize complicated front-end-of-line layer stacks and deploy multi-patterning lithography on many masks. This means more and more masks are required for advanced processes.
The increase in density, plus the added number and complexity of process layers means that as designers migrate from older nodes to 7nm and 5nm physical verification has the potential to be more and more of a bottleneck for tapeout. Expect complaints such as:
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