Achieving eFPGA Timing Closure In An ASIC

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems Engineering, discussed at the Design Automation Conference in June, sharing is also key when it comes to closing timing with embedded FPGAs (eFPGAs).

With an eFPGA, such as Achronix’s Speedcore IP, the task of closing timing is owned by two people: the ASIC designer responsible for the design in the host ASIC and the FPGA designer responsible for the design targeting the FPGA. This situation is analogous to how timing is closed on a PCB with an FPGA where both designers need to cooperate and share the timing arc. Of course, the FPGA design may change long after the board design is complete.

The programmable block of an eFPGA may be inserted anywhere inside an ASIC, meaning that individual eFPGA ports may connect to other blocks within the ASIC or to buffers connecting to external pins. Further complicating the process is the fact that the design host in the eFPGA can and will change over time, possibly years after the ASIC was designed.

Rather than leaving it to design teams to develop a process, it helps to have one defined methodology for achieving timing closure as well as support for industry-standard timing analysis tools. As Orthner explained (a video of his talk is here), there are two timing models or modes available to the design team: simple and advanced.

Simple mode
In the simple timing mode, the timing between the IP in the host ASIC outside the Speedcore instance terminates at the register in the interface cluster in its boundary ring as shown below. In this scenario, delays are not dependent on the design hosted in the instance. With simple mode, timing closure is performed by the SoC supplier using standard tools such as Synopsys’ PrimeTime where the .lib file represents timing data (setup/hold/clock-to-q) to/from boundary flip-flops. Achronix ACE design tools may require clock insertion delay information in this scenario.

Figure 1: Timing between the IP in the host ASIC outside the instance terminates at the register in the interface cluster in the boundary ring. Source: Achronix

Advanced mode
This timing closure scenario is more complex because the Speedcore eFPGA and the IP outside is shared between the SoC supplier and ACE design tools as shown below. With advanced mode, .lib files do not contain delays to a specific flip-flop in the fabric, but rather represent a range of flip-flops, chosen such that timing closure using the hardware .lib files correlate to timing closure in the design tool. The .lib files still contain one setup/hold/clk-to-q value for each pin. In this mode, final timing sign-off comes from the tool, completed by using a suite of user designs containing critical paths representative of actual end-user designs.

Figure 2: Timing closure between the eFPGA and the outside IP is complex because it is shared between the SoC supplier and design tools. Source: Achronix

Timing closure is an iterative process
Timing closure consists of a basic set of steps:

1. Choose a target frequency and determine how much of the clock cycle will be used by and shared with the ASIC logic.
2. Run ASIC timing closure using an industry-standard tool such as Synopsys’ PrimeTime with the Achronix-provided budgetary .lib
3. Extract the ASIC portion of the delays on each wire and provide them to the design tool via constraint files, following the template provided by Achronix.
4. Run a suite of representative designs through the design tool to confirm that timing closure has been met for each one.
5. If timing cannot be met for one or more of these designs, modify the FPGA design or return to step 1.

The bonus is that the selection of timing mode does not need to be made at the time the ASIC is designed. It can be left up the FPGA designer. To learn more, see the video located here.