Achieving Successful Multi-Die Signoff

Multi-die designs leveraging 2.5D and 3D technologies are becoming crucial for various electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile devices. These designs allow the integration of dies from different foundries and technology nodes, enhancing density and interconnect speeds beyond traditional discrete dies. However, they also introduce new challenges in timing, power, and physical signoff. This is addressed in the white paper ‘Achieving Successful Timing, Power, and Physical Signoff for Multi-Die Designs,’ along with advanced electronic design automation (EDA) solutions.

Multi-die signoff overview

Traditional 2D timing, checking, and power analysis tools are inadequate for multi-die signoff. Signals crossing between dies pass through multiple stacked layers, requiring consideration of delays through these layers for static timing analysis. This necessitates new requirements for physical verification and parasitic extraction. Power calculations must combine results for all dies, and physical checks like design rule checking (DRC) and layout versus schematic (LVS) verification must consider the entire stack.

Synopsys StarRC for parasitic extraction creates a virtual interface die stack for inter-die coupling. The extracted parasitics are used by Synopsys PrimeTime for static timing analysis and Synopsys PrimePower for full-chip design power analysis. DRC and LVS checks are performed by Synopsys IC Validator, and timing, power, and physical signoff are integrated with Synopsys 3DIC Compiler, forming a comprehensive flow for multi-die signoff.

Synopsys multi-die signoff solution.

Multi-die extraction and timing signoff

Static timing analysis (STA) in Synopsys PrimeTime relies on accurate parasitic extraction by Synopsys StarRC, handling all parts of the multi-die package, including through-silicon vias (TSVs), micro bumps, interposers, and stacking. Synopsys StarRC uses an RLCK model (resistance, inductance, capacitance, mutual inductance) for precision beyond traditional R and C values. Key features include auto-generation of Virtual Interface Blocks (VIBs), auto-technology and layer mapping, and support for the latest 3Dblox standard.

Multi-die STA faces challenges with worst-case and best-case timing paths crossing dies at different process, voltage, and temperature (PVT) corners, potentially leading to excessive resource consumption. Synopsys PrimeTime addresses this with HyperScale technology and distributed multi-scenario analysis, enabling efficient die modeling and reducing overall design model complexity.

Multi-die power signoff

The parasitics extracted by Synopsys StarRC also support power analysis and signoff. Synopsys PrimePower calculates power for the entire multi-die stack through a three-step flow: individual die power analysis in the system context, power annotation to hyperscale models, and power aggregation for all dies, including interface logic between them. Thermal analysis, crucial for multi-die designs, is tightly integrated with Ansys products, the industry standard for thermal management.

Multi-die physical signoff

For multi-die designs, DRC and LVS checks are performed on individual dies and the structures connecting them. Synopsys IC Validator enables inter-die DRC and LVS checks, including die placement, bump alignment, inter-die connectivity, and shorts/opens. These checks can be run from within Synopsys 3DIC Compiler, which allows in-design verification and debugging, providing a 3D view of DRC/LVS checks.

Summary

Multi-die designs, driven by disaggregation of large dies and aggregation of discrete chips, offer significant advantages in flexibility, density, power efficiency, and communication bandwidth. Traditional 2D EDA flows are insufficient for multi-die designs, requiring advanced parasitic extraction, power analysis, and physical checks. Synopsys provides a comprehensive solution for multi-die signoff, enabling designers and verification engineers to handle complex designs confidently.

For more information, download the Achieving Successful Timing, Power, and Physical Signoff for Multi-Die Designs white paper.