Alchip Minimizes Dynamic Power For High-Performance Computing ASICs

How a fabless chipmaker successfully reduced power consumption within its fishbone clock tree methodology.


Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design flow? This whitepaper documents their journey and the successful results of the project.

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