The benefits of C-based behavioral synthesis over RTL-base methods for system LSI or SoC design.
This paper presents the benefits of C language-based behavioral synthesis design methodology over traditional RTL-based methods for System LSI, or SoC designs. A comprehensive C-based tool flow, based on CyberWorkBench®, developed during the last twenty years at NEC’s R&D laboratories is introduced. This includes behavioral synthesis and formal verification and hardware-software co-simulation of entire complex SoC. First we introduce the “All-in-C” concept based on CyberWorkBench. Then we discuss the behavioral synthesis for various types of circuits and examine the advantages of behavioral synthesis on the hand of commercial ICs. We show that currently entire SoCs are created using this flow in a fraction of the time taken by traditional approaches. Behavioral IP and C-based configurable processor synthesis and automatic architecture exploration is explained next. At the end we demonstrate a real world example of a mobile phone SoC where most of the modules are synthesized from C descriptions using CyberWorkBench.
To read more, click https://www.aldec.com/en/downloads/private/622.
The more compute power, the better. But what’s the best way to get there?
Yield rises with mask protection; multiple sources will likely reduce costs.
More heterogeneous designs and packaging options add challenges across the supply chain, from design to manufacturing and into the field.
CNTs promise big performance improvements, but achieving consistency and replacing incumbent technologies will be difficult.
Computational storage approaches push power and latency tradeoffs.
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
An upbeat industry at the start of the year met one of its biggest challenges, but instead of being a headwind, it quickly turned into a tailwind.
The backbone of computing architecture for 75 years is being supplanted by more efficient, less general compute architectures.
How long a chip is supposed to function raises questions design teams need to think about, including how much they trust aging models.
New interconnects and processes will be required to reach the next process nodes.
After failing in the fab race, the country has started focusing on less capital-intensive segments.
Servers today feature one or two x86 chips, or maybe an Arm processor. In 5 or 10 years they will feature many more.
SRC’s new CEO sheds some light on next-gen projects involving everything from chiplets to hyperdimensional computing and mixed reality.
Necessary cookies are absolutely essential for the website to function properly. This category only includes cookies that ensures basic functionalities and security features of the website. These cookies do not store any personal information.
Any cookies that may not be particularly necessary for the website to function and is used specifically to collect user personal data via analytics, ads, other embedded contents are termed as non-necessary cookies. It is mandatory to procure user consent prior to running these cookies on your website.
Leave a Reply