An Inside Look At UPF 4.0

Energy and power efficiency are increasingly important in today’s products, and the additional complexity in new architectures to incorporate competitive power management schemes has magnified the need for newer and better methodologies for the verification, implementation, and reuse of power intent specifications.

This is the focus of the new IEEE 1801-2024 Unified Power Format (UPF) 4.0 standard, introduced at this year’s DVCon. The standard officially was published on March 4 by the IEEE.  A workshop entitled, “Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent,” was presented at DVCon by John Decker and Daniel Cross from Cadence, Amit Srivastava from Synopsys, and Lakshmanan Balasubramanian from Texas Instruments, followed by specific area presentations^[1,2,3,4] delivered the next day.

The impetus behind power intent specification is the need to separate the information for partitioning a design into separate power domains from the functional requirements. This enables engineers to code RTL without having to specifically code in voltage level shifters and isolation cells that could change for the same functional block used in a different power architecture. This way the same RTL block can be re-used in multiple power management schemes with the power intent for each scheme specified in separate UPF files.

The major objectives of the new UPF 4.0 version include:

• Enabling accurate modeling of state retention;
• Enabling low power simulation with mixed-signal features like real number modeling;
• Enhancing IP design reuse with refinable macros;
• Improving the successive refinement flow, and
• Addressing more than 200 items for improvement requests.

Over time, advances in state retention cells exposed limitations in earlier versions of the UPF standard and enhancements were needed to handle the more complex clock, setup, and retention relationships enabled by these newer cells. Improved modeling in UPF 4.0^[3] also makes earlier issue detection possible and new improvements were incorporated with an eye towards providing flexibility for adding future functionality.

New for UPF 4.0^[2] are Value Conversion Methods (VCMs). Value Conversion Tables (VCTs) are now legacy, and they continue to work, but designers are strongly encouraged to migrate to VCMs. VCM extends and enhances VCT, and VCT functionality is now a subset of VCMs. (Annex I in the new UPF 4.0 standard includes a VCM example.) VCMs provide a richer and more flexible mechanism to translate between UPF supply nets and HDL. VCMs enable connecting UPF supply nets to integer, enum, real, and user-defined net types (UDN). Only UPF supply nets can be connected to these methods, but not logic nets or supply sets.

Soft IPs (SIPs) present challenges in bottom-up verification flows. Each SIP can have unique power rules and higher-level implementation requires power intent updates. After modifying SIPs, revalidation requires additional time and resources and not revalidating risks introducing bugs that aren’t detected. The UPF 3.1 fix was Soft Macros which are good for implementation but too rigid for pre-verified SIPs. Refinable Macros in UPF 4.0^[1] have refinable terminal boundaries, tool-enforced safety with non-intrusive power intent updates and the original IP UPF remains untouched. This enables system-level optimization during implementation and still supports bottom-up verification.

New with the release of UPF 4.0 is an IEEE SA Open site that now includes clean ascii text files for the SystemVerilog and VHDL packages inside the standard as well as the files for the UPF SoC example in Annex E. The hope is that this will make it easier for the community in general to use this material from within the standard and provide files that EDA vendors can incorporate into their regression tests to speed the development of tool support for the new standard.

Looking beyond 1801-2024 we can expect continued innovation on mixed signal design and interfacing to enable supply networks to carry information about power generation and consumption, bi-directional supply ports, features to improve static checking of designs with mixed analog/digital components and power modeling in the context of mixed signal integrations. Improvements for supporting the continued development of new technology cells, for information models beyond SystemVerilog and VHDL as well as ease of use and specification are all under discussion.

Once again, the latest version, 1801-2024 – IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, is available free of charge through the IEEE GET program. An official announcement from Accellera was made here on March 19, 2025

UPF 1.0 was first published by Accellera in 2007 and has been published by the IEEE since 1801-2009 (UPF 2.0) in 2009. There’s a more detailed description of the early years of the Unified Power Format at A Brief History Of Power Formats written in 2012.  Figure 1, below, provides a broader overview of the progression of the 1801 UPF standard. At six years between 1801-2018 (UPF 3.1) and 1801-2024, this is the longest period between successive new versions of the standard.

Fig. 1: Evolution of IEEE 1801. Source: DVCon/Accellera

Sources

1. A. Srivastava, et al., “Refinable Macros and Terminal Boundaries in UPF 4.0: Empowering Soft IPs of the Future,” DVCon, February 25, 2025
2. D. Cross, “Applications for UPF HDL Supply Tunneling in Mixed Signal Design,” DVCon, February 25, 2025
3. L. Balasubramanian, et al., “Future Proofing Power Intent Specification through Unified Power Format 4.0 for Evolving Advanced State Retention Strategies,” DVCon, February 25, 2025
4. P. Khondkar, “What’s New in IEEE 1801 and Why you Need to Know Now?,” DVCon, February 25, 2025