What Happened To Portable Stimulus?


In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Week In Review: Design, Low Power


It’s earnings season. Arm, Cadence, Synopsys, Siemens (consolidated), Rambus, and Renesas reported quarterly results over the past couple weeks. All posted year-over-year revenue growth, despite an overall challenging macroeconomic climate. A roundup of all the chip industry earnings reports from the past several weeks can be found here. The edge computing market is projected to jump to al... » read more

What Does 2023 Have In Store For Chip Design?


Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Scaling Simulation


Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn't received the attention and research it deserves, causing a stagnation in performance. Others disagree, noting that design sizes have increased by orders of magnitude while design times have shrunk, pointing to simulation remaining a suitable tool for the job... » read more

Standards, Open Source, and Tools


Experts at the Table: Semiconductor Engineering discussed what open source verification means today and what it should evolve into with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardware engineer... » read more

An Industry Under Siege


The coronavirus is taking a big toll on the semiconductor industry's unquenchable thirst for new information. The longer it lasts, the more the industry will have to resort to technology — some new, some old — to continue moving forward. Over the past couple weeks, conferences and trade shows have been postponed or outright canceled. Synopsys, Cadence and Intel pulled out of DVCon at the... » read more

Abstracting Abstracter Abstractions In Functional Verification


I heard a clear three-part message during DVCon at the end of February: verification engineers must abstractly embrace the abstract idea of abstracting abstract abstraction through higher levels of abstraction; we overuse the word abstract to emphasize the value of whatever verification technique we happen to be talking about; and the key to new abstractions is using Portable Stimulu... » read more

Verification And Validation Brothers


At DVCon this year, Doug Amos took the stage for the [getentity id="22017" e_name="Mentor, a Siemens Business"] sponsored lunch presentation. For those of you who were there but decided to skip the lunch, expecting the traditional forced sales pitch, you made a mistake. Amos is one of those rare people who know how to inject humor, teaching and marketing into a single presentation such that the... » read more

The Week In Review: Design


Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

The Week In Review: Design


Tools & IP Arm unveiled a new suite of IP focused on machine learning for edge devices. Currently dubbed Project Trillium, it includes the Arm ML processor, the second-generation Arm Object Detection (OD) processor, and open-source Arm NN software. The ML processor provides more than 4.6 TOPs in mobile environments with efficiency of 3 TOPs/W. People detection is a focus of the OD processo... » read more

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