Week In Review: Design, Low Power

Latest earnings; edge market; memory demand for AI; HW defects causing silent errors; RISC-V for HPC; new verification IP; Intel’s latest; new addition to DAC.


It’s earnings season. Arm, Cadence, Synopsys, Siemens (consolidated), Rambus, and Renesas reported quarterly results over the past couple weeks. All posted year-over-year revenue growth, despite an overall challenging macroeconomic climate. A roundup of all the chip industry earnings reports from the past several weeks can be found here.

The edge computing market is projected to jump to almost $317 billion in 2026, up from $208 billion in 2023, according to IDC. Among companies driving the largest investments are content delivery networks and those involved with virtual network functions and multi-access edge computing (MEC).

Natural-language AI technologies, such as ChatGPT, are expected to boost demand for memory at Samsung and other memory makers. In its earnings call, Samsung executives noted high-performance HBM, which is connected directly to CPUs and accelerators, and high-density server DRAM, which is used for AI learning, would drive long-term demand.

HBM demand is growing due to a spike in the amount of data that needs to be processed quickly. Big reductions in power are possible if that processing can be moved closer to the HBM modules, and if more can be done in each compute cycle without sending data back and forth to memory as frequently.

Spintronic-based racetrack memories (RTMs) are garnering attention due to storage capacity, reduced energy per operation, and high write endurance. Researchers at University of Calabria and TU Dresden have developed an “Efficient Racetrack Memory Emulation System based on FPGA.”

Faster, more reliable chips
The semiconductor industry is urgently pursuing design, monitoring, and testing strategies to help identify and eliminate hardware defects that can cause catastrophic errors. These subtle IC defects in data center CPUs, called Silent Data Errors (SDEs), are difficult to detect during manufacturing. Some of these errors may need to be caught in the field, which would require SoC design teams to include on-die monitors for path timing, local voltage, temperature, and aging effects that can impact performance.

Intel launched its new Xeon W-3400 and W-2400 desktop workstation processors, which incorporate Embedded Multi-Die Interconnect Bridge (EMIB) interconnects. The new processors include up to 56 cores in a single socket, up to 112 CPU PCIe Gen 5.0 lanes, DDR5 RDIMM memory support, and Wi-Fi 6E. Price ranges from $359 to $5,889.

Vint Cerf, considered one of the fathers of the internet, called ChatGPT snake oil. “It’s like a salad shooter — you know, how the lettuce goes all over everywhere,” he said. “The facts are all over everywhere, and it mixes them together because it doesn’t know any better.”

Still, there is optimism when it comes to AI in general. “The AI revolution is upon us,” said John Hennessy, chairman of Google’s parent company, Alphabet. “It’s stunning. It’s awakened in everybody a sense that maybe the singularity … this turning point where computers really are more capable than humans, is closer than we thought.”

MIT and MIT-IBM Watson AI Lab developed a technique that enables a model to quantify the level of confidence in a prediction with much less compute resources that other methods.

The industry is exploring RISC-V-based supercomputing and high-performance computing. Questions remain about the software ecosystem, or whether the chips, boards, and systems are reliable enough. And there are both business and technical problems, with the business issues being the most difficult. To this end,  the RISC-V HPC Special Interest Group is organizing a workshop at ISC23, a high-performance computing (HPC) conference in Hamburg, Germany, on May 25.

Products & Deals
Cadence unveiled 13 new verification IP (VIP) solutions that allow for fast and comprehensive verification and meet the specs for the latest standard protocols, including Arm AMBA 5 CHI-f, UCIe, GDDR7, DDR5 DIMM, MIPI A-PHY and SoundWire I3S, and USB4 2.0 interfaces.

Keysight said its 5G Open Radio Access Network (O-RAN) Solutions portfolio enabled Pegatron to obtain the first O-RAN ALLIANCE End-to-End (E2E) system integration badge from Auray Open Testing and Integration Center (OTIC) and Security Lab.

Intel and NVIDIA are pairing the latest Xeon processors with 6000 Ada Generation GPUs and ConnectX-6 SmartNICs. Target markets include Metaverse applications, digital twins, data science, among others.

The U.S. Naval Postgraduate School (NPS) and Qualcomm are teaming up to research 5G wireless communications, cloud/edge computing, artificial intelligence, hardware development platforms, and associated technologies.

This year the Design Automation Conference will showcase a zone on the exhibition floor dedicated to the AI hardware ecosystem. DAC is encouraging companies that focus on the following areas to exhibit:

  • AI infrastructure in data centers for training and inference at scale
  • Edge computing applications for AI accelerators, TinyML systems and hardware
  • AI’s impact on memory, storage and networking
  • ML model-hardware co-design, robustness and re-programmability, model standardization and interoperability
  • AI chip design and commercialization: design, testing and manufacturing, and routes-to-market

Bookmark a full lineup of this year’s chip industry conferences here.  Upcoming events in February include:

  • ISSCC 2023: Feb. 19 –23 in San Francisco, CA
  • Phil Kaufman Award & Banquet: Feb.23 in San Jose, CA
  • HPCA 2023: Feb. 25 – Mar. 1 in Montreal, QC, Canada
  • DVCon U.S.: Feb. 27 – Mar. 2, in San Jose, CA

Further Reading
Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • Is RISC-V Ready For Supercomputing?
  • Disaggregating And Extending Operating Systems
  • Chiplets Taking Root As Silicon-Proven Hard IP
  • Power Issues Causing More Respins At 7nm And Below
  • CXL Picks Up Steam In Data Centers
  • Selecting The Right RISC-V Core
  • Multi-Die Integration

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