An Introduction To Reducing Dynamic Power

Dynamic power becomes the dominant contributor to power consumption as designs move to finFET technology.


In the past few blogs we have been primarily talking about UPF and applying the Successive Refinement process to save power. But, this process addresses leakage power. In this session we want to talk about how to save dynamic power. As designs move to finFET technology, dynamic power is the dominant contributor to power consumption.

Power consumption trend.

I recently sat down with my colleague Abhishek Ranjan, who is the director of engineering for the PowerPro RTL Low-Power Platform at Mentor Graphics, to explore saving dynamic power.


Q: Abhishek, can you give a short introduction into what saving dynamic power means?

Ranjan: UPF has primarily been used to facilitate power gating for leakage power. However, its primary use is for defining voltage domains. One of the reasons for specifying different voltage domains is to negotiate power-performance trade-offs. Higher voltage gives more speed, but at the cost of more dynamic power (1/2 C V2 f). Voltage has a square effect on power. So, dynamic power reduction starts with planning appropriate voltage levels for various blocks in the design.

Dynamic power is primarily affected by activity. The more work that the design is doing, the more energy it ends up needing. As the speed to complete work in the design increases, the power required increases. To save dynamic power, either you slow down the design (reduce clock speeds), try to reduce voltages, or attempt to cut down design activity. Reducing capacitances in the design is another important aspect of saving power, which typically can be accomplished with efficient implementation or by tweaking processes.

Q: Interesting.  It seems that most companies try to find ways to reduce power consumption primarily during the implementation/physical design stages. But it seems that you could save more power if you worked at the RTL or above. Can you comment on what you see out there for power saving results comparing these different approaches?

Ranjan: Absolutely right. Designers have been leaving power minimization to implementation/physical tools. However, by then, all important architectural and micro-architectural decisions about the design have been frozen. Physical tools can influence power in a very limited way. These tools are not able to make sweeping changes to your design architecture in order to save power. Techniques like cell sizing, pin swapping, and Vth selection are used by physical tools, but these techniques typically reduce power only by a small percentage.

As mentioned earlier, dynamic power is about choosing clock speeds and voltages and looking at activity. These factors can be addressed better at higher levels of design abstraction. Typically, design architects do a fairly good job of deciding voltages and clock speeds. However, reducing activity (especially unnecessary activity) has not been addressed well so far. Many of these reductions require micro-architectural changes (such as FSM re-encoding, block-level clock gating, memory gating, memory banking, and bypassing memory accesses) that require more understanding of the design functionality. These changes are better performed by the designers that write the RTL.

Q: OK, so designers really need to be thinking about reducing power at the RTL to get the maximum results.  What are the most popular techniques that are used today to reduce dynamic power?

Ranjan: Absolutely. Decisions made at RTL have a much bigger impact on design power than decisions made later in the design process. RTL designers heavily rely on clock gating to cut down on clock toggles. This is, by far, the most popular technique to reduce dynamic power. Some other techniques that RTL designers use are data-gating and flop cloning/sharing.


Cloning flop technique.

Q: Are there other techniques that are perhaps more micro-architectural that could save you even more power?

Ranjan: Yes. To have a more profound impact on power, RTL designers need to make more and more coarse-grained (micro-architectural) changes in their designs. For example, they can employ block-level clock gating, convert register chains to circular buffers, gate memories, bypass memory accesses, perform retiming, and use operator shielding. These techniques cut down dynamic power significantly.

Q: Those techniques all sound very effective. Are they easy or difficult to do? What debug techniques are available for analyzing power consumption, finding the leaks, and knowing how to address them?

Ranjan: Unfortunately, these techniques are not as widely used as they should be. There are two primary reasons for that. One is that it is not easy to know that these opportunities exist in the design. Secondly, it is not easy to know how much power reduction would happen by making such changes. Usually, designers rely on their experience or intuition to make design changes. They load up the waveforms and try to estimate where redundant activity could be occurring in their designs. Then, depending on the area of such activity, they try to assess which technique could cut down the wasted activity. For a general RTL designer, this is too much to ask for. As a result, a lot of power savings are left on the table.

Q: We see companies that have dedicated power experts that take care of power and in others it is the RTL designer’s responsibility. Can you comment on what you see at various companies, how they approach power reduction, and which approach is most effective?

Ranjan: We have seen both. However, at a majority of the companies, the job of power reduction is left to power experts. These experts have built up knowledge and methodologies over many years which they repeatedly apply to designs in their groups. This approach is very narrow and it not scalable across multiple groups the company.

Companies have begun to realize the limitations of this approach. More and more RTL designers are being tasked with addressing power as they design. Ideally, this is how it should be. The person that understands the design is best suited to optimize it for power.

Q: How does a tool like PowerPro help the designer perform this job?

Ranjan: Through several years of engagement with power-savvy designers, it is clear that traditional ways of performing power reduction are no longer practical. Migration to FinFET poses an ever increasing challenge for dynamic power. To maintain a competitive edge, relying solely on power experts for reducing power is no longer sufficient. Companies are losing out to rivals purely on power.

Simply reporting power numbers for designs is no longer relevant. Power analysis is an important step, but it does not really do anything for saving power. Again, it falls back to the expertise of individual designers and how they interpret the tool reports to optimize the design for power.

What RTL designers need is guidance about where power can be saved in the design. They need concrete evidence of the scope for optimizations (for example, block-level clock-gating, shift-register-to-circular buffer, memory caching, and reset removal) in their designs and the associated power savings. PowerPro provides many micro-architectural and fine-grained optimization possibilities in the design and it presents the actual power savings associated with each change. This minimizes the time spent making design decisions versus manual techniques. Based on the PowerPro suggestions, designers can make changes according to their design schedules. If there is enough time in schedule, they can act on all suggestions. If the time is limited, designers can pick from the best suggestions. This flexibility is the key to adopting PowerPro in design flows.

One other key component of power optimization is the ability to explore power for various kinds of changes: mode of operation, clock frequency, operating voltage, and process technology, for example. The suggested optimizations should work across all of these parameters. PowerPro lets designers explore a change in simulation profile, voltage, clock speed, and the design itself. Many of these changes are evaluated concurrently within PowerPro. So, an exploration task that would have otherwise taken weeks to finish, can now be accomplished in a matter of hours. This productivity improvement makes PowerPro a very attractive addition to design flows.


PowerPro power exploration.

Q: PowerPro has been helping designers reduce power for a long time and getting significant results. Why is it different when it comes to finding the most power savings?

Ranjan: The underlying technology to detect power redundancies is formal analysis. PowerPro performs a deep sequential analysis of the design to figure out redundancies in memory accesses, register loading, and datapath computations. The ability to suggest changes based on sequential exploration, makes PowerPro far superior to competing technology in the market. PowerPro provides support for all aspects of the design flow: writing out optimized RTL, ECO, and verification. Designers are confident that they can accept all suggestions coming from PowerPro and that there will not be any adverse impact on their delivery schedule.

My thanks to Abhishek for introducing the design considerations for dynamic power. To learn more about dynamic power and PowerPro, check out the video – Solving the FinFET Dynamic Power Challenge at RTL.

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