Architects: How To Get The Most Out Of eFPGA

At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA.

1. Use as little eFPGA as possible. eFPGA is much larger in area than hard-wired ASIC, so only put what must be reconfigurable into eFPGA. This sounds easy, but it is not. It requires someone thinking hard about the boundary between fixed and reconfigurable. And it requires thinking hard about what kind of reconfigurability may be needed in the future and making tradeoffs between more and less reconfigurability and more and less area for eFPGA.

2. Don’t assume you should have just one block of eFPGA. We see customer designs that have two, three, four and even more blocks of eFPGA. One customer, for example, showed a slide at a recent public session where they have four blocks of eFPGA: one for reconfigurable serial I/O to handle different standards; one for the digital protocol logic on a high speed PHY; one for an encryption accelerator to handle multiple standards; and a fourth for a general accelerator for their processor. Each of the eFPGA had different array sizes, different connections to the rest of the chip, and different needs for DSP and RAM options. Some vendors, like Flex Logix, will provide as many different eFPGA sizes and options as you need for one design for one fixed license fee.

3. Don’t assume that an eFPGA needs to be tens of thousands of LUTs. There are applications for just hundreds of LUTs where 256 or 512 bit buses running at 600MHz+ can be brought into a few EFLX150 cores (high I/O to LUT ratio) to do high speed comparisons and simple math on selected fields in a programmable fashion enabling the chip to be handle future protocols or data center needs.

4. Don’t assume eFPGA is only for leading edge nodes. We have ported EFLX to Sandia’s proprietary 180nm process. We can provide eFPGA on any digital CMOS process and at very affordable prices. We don’t make the first customer on a node pay for all of the development – we’ll only charge you for one design even if we lose money because we know once you do one eFPGA chip, you’ll do more, so we’ll make money over time.

5. Don’t assume eFPGA is a niche. We have one customer now who is doing 5 designs with us and says they now expect to use eFPGA on the majority of chip designs they do from now on. They hadn’t expected this when they started but learned eFPGA is both easier than they thought and more useful than they thought.