Author's Latest Posts

Aldec HES Emulation Integration With Imperas OVP
By Aldec - 29 Jun, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

Virtual Modeling With Aldec And Imperas
By Aldec - 25 May, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

SoC Verification Made Easy
By Aldec - 27 Apr, 2016 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, there-fore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This docu... » read more

Q&A With FAA DO-254
By Aldec - 23 Mar, 2016 - Comments: 0

Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly. To read more, c... » read more

Managing Validation And Verification Abstract Activities For DO-254
By Aldec - 24 Feb, 2016 - Comments: 0

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

Finding CDC Issues Before They Find You
By Aldec - 27 Jan, 2016 - Comments: 0

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

C-Based SoC Design Flow And EDA Tools
By Aldec - 21 Dec, 2015 - Comments: 0

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment t... » read more

ARM Cortex SoC Prototyping Platform For Industrial Applications
By Aldec - 23 Nov, 2015 - Comments: 0

Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as the Aldec HES-7, provide a platform for designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this ... » read more

All-in-C Behavioral Synthesis And Verification
By Aldec - 28 Oct, 2015 - Comments: 0

This paper presents the benefits of C language-based behavioral synthesis design methodology over traditional RTL-based methods for System LSI, or SoC designs. A comprehensive C-based tool flow, based on CyberWorkBench®, developed during the last twenty years at NEC’s R&D laboratories is introduced. This includes behavioral synthesis and formal verification and hardware-software co-simulatio... » read more

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