C-Based SoC Design Flow And EDA Tools

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis and verification tools. A high-level synthesis system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of mixed-level hardware/software co-simulator, formal and semi- formal verifiers, and test-bench generators. The verification tools are tightly integrated with the high-level synthesis system and take advantage of information from the synthesis system. Then, we discuss the possibility of incorporating physical design feature into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

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