Anne Meixner

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Anne Meixner is a contributing editor at Semiconductor Engineering. She has 30+ years in the semiconductor industry. She became fascinated by defects in the semiconductor manufacturing process as a young engineer at IBM. Over that period, she has focused on test methodology with emphasis on mixed-signal and analog DFT and test. As a technical communicator she takes complex ideas and explains them in consumable understandable pieces. Meixner has worked at IBM, Carnegie Mellon University and Intel. She holds three U.S. patents and her peers have recognized her work with two best papers at IEEE International Test Conference. She founded The Engineers’ Daughter in 2015 to consult on semiconductor testing and to coach engineers.

Author's Latest Posts

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Geo-Spatial Outlier Detection
By Anne Meixner - 19 Jul, 2021 - Comments: 0

Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

Sharing Secure Chip Data For Analytics
By Anne Meixner - 06 Apr, 2021 - Comments: 0

New approaches and standards are being developed to securely share manufacturing and test data across the supply chain, moves that have long been considered critical to the reliability of end devices and faster time to yield and profitability. It will take time before these methods become widespread in the IC supply chain. But there is increasing agreement these kinds of measures are essenti... » read more

Hunting For Open Defects In Advanced Packages
By Anne Meixner - 17 Mar, 2021 - Comments: 5

Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Cloud Vs. On-Premise Analytics
By Anne Meixner - 09 Mar, 2021 - Comments: 2

The immense and growing volume of data generated in chip manufacturing is forcing chipmakers to rethink where to process and store that data. For fabs and OSATs, this decision is not one to be taken lightly. The proprietary nature of yield, performance, and other data, and corporate policies to retain tight control of that data, have so far limited outsourcing to the cloud. But as the amount... » read more

Part Average Tests For Auto ICs Not Good Enough
By Anne Meixner - 24 Feb, 2021 - Comments: 0

Part Average Testing (PAT) has long been used in automotive. For some semiconductor technologies it remains viable, while for others it is no longer good enough. Automakers are bracing for chips developed at advanced process nodes with much trepidation. Tight control of their supply chains and a reliance upon mature electronic processes so far have enabled them to increase electronic compone... » read more

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