Author's Latest Posts

Improvement Of EUV Si Hardmask Performance Through Wet Chemistry Functionalization
By Brewer Science - 20 May, 2021 - Comments: 0

In EUV lithography, spin-on silicon hardmasks have been widely used not only as etch transfer layers, but also as assist layers to enhance the lithographic performance of resist. In this study, we demonstrate a novel approach to functionalize spin-on silicon hardmasks by hybridizing them with functional groups through a sol-gel approach. By varying the concentration and type of the functional g... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials
By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
By Brewer Science - 17 Feb, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonstrat... » read more

Improving EUV Underlayer Coating Defectivity Using Point-Of-Use Filtration
By Brewer Science - 18 Nov, 2020 - Comments: 0

Authors: Aiwen Wu (Entegris, Inc. — United States), Hareen Bayana (Entegris GmbH — Germany), Philippe Foubert (imec — Belgium), Andrea Chacko and Douglas Guererro (Brewer Science, Inc. — United States). This paper describes efforts to leverage different filtration parameters, including retention ratings and membrane materials, to understand their impact on EUV underlayer coating defe... » read more

Development Of Planarizing Spin-On Carbon Materials For High-Temperature Processes
By Brewer Science - 20 Aug, 2020 - Comments: 0

Multilayer lithography is used for advanced semiconductor processes to pattern complex structures. As more and more procedures incorporate a high-temperature process, such as chemical vapor deposition (CVD), the need for thermally stable materials increases. For certain applications, a spin-on carbon (SOC) layer under the CVD layer is required to survive through a high-temperature process. ... » read more

Super Planarizing Material For Trench And Via Arrays
By Brewer Science - 21 May, 2020 - Comments: 0

As device design scales and becomes more complex, fine control of patterning and transfer steps is integral. Planarization of deep trenches and via arrays has always been a challenge. Aspect ratios continue to increase while critical dimensions shrink, and typical trench fill schemes are no longer able to meet the fill and planarization requirements. Traditional design of spin-on carbon (SOC) m... » read more

Thin Film Characterization For Advanced Patterning
By Brewer Science - 18 Mar, 2020 - Comments: 0

Authors: Zhimin Zhu; Xianggui Ye; Sean Simmons; Catherine Frank; Tim Limmer; James Lamb Brewer Science, Inc. (United States) A variable-angle spectroscopic ellipsometer (VASE) is an essential tool for measuring the thickness of a thin film, as well as its n and k optical parameters. However, for films thinner than 10 nm, precise measurement is very challenging. In this paper, the root cause... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes
By Brewer Science - 14 Aug, 2019 - Comments: 0

Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging
By Brewer Science - 11 Jun, 2018 - Comments: 0

The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

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