Author's Latest Posts

A Program Manager’s Guide to Successful Integrated Circuit Verification

By Cadence - 12 Apr, 2017 - Comments: 0

Accurately monitoring progress on complex integrated circuit (IC) designs has become more difficult as the designs have increased in complexity, leading to surprises from backwards-looking reporting and management processes that do not forewarn coming crises. The Cadence Metric-Driven Verification Methodology provides a more uniform and standardized method of reporting progress towards closure ... » read more

Massive SoC Designs Open Doors To New Era In Simulation

By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Power-Aware Analysis Solution

By Cadence - 25 Jan, 2017 - Comments: 0

By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flow, and examining what is employed in Cadence Sigrity power and signal simulations using the SPEED2000, PowerSI, Transistor-to-Behavioral Model Conversion (T2BTM), and SystemSI tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also ... » read more

DO-254 Explained

By Cadence - 21 Dec, 2016 - Comments: 0

This white paper, the first in a series of DO-254-related white papers, will explore the high-level concepts and activities within the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specification, why they exist, and what they mean. In this paper, we will explore the safety-related concepts of requirements traceability, design assurance levels, the overall DO-254-compliant fl... » read more

How High-Level Synthesis Was Used to Develop An Image-Processing IP Design From C++ Source Code

By Cadence - 07 Dec, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Accelerating DO-254 Approval

By Cadence - 23 Nov, 2016 - Comments: 0

This white paper explores software tools as they relate to meeting the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specifications, and what steps must be performed in order to use your typical design automation tools such as simulation, synthesis, etc. In this paper, we will explore how DO-254 views tools, learn which tools receive the highest scrutiny and why, and how to ... » read more

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP

By Cadence - 09 Nov, 2016 - Comments: 0

The proposed IEEE 802.11ah wireless networking protocol is designed to meet the requirements of Internet of Things (IoT) connectivity, providing the bit rate, security, and low power required for these types of connected devices. Design requirements for 802.11ah access point and clients vary widely, even though all implement the same mathematical algorithm. In this paper, we will discuss how... » read more

Massively Parallel Electrically Aware Design

By Cadence - 26 Oct, 2016 - Comments: 0

In-design verification is opening new opportunities to shorten design cycles and maximize circuit performance. Whereas physical verification has traditionally required a tradeoff between accuracy and performance for larger designs, recent advances in large-scale distributed computing may offer an alternative. Cloud infrastructure needs are pushing the industry toward larger multi-core server ar... » read more

Addressing Memory Characterization Capacity And Throughput Requirements With Dynamic Partitioning

By Cadence - 12 Oct, 2016 - Comments: 0

Typical memory characterization techniques using memory compilers and instance-specific memories have a number of tradeoffs—development time, accuracy, performance, and more. Ad-hoc instance-specific characterization methods such as dynamic simulation, transistor-level static timing analysis, and divide-and-conquer suffer from multiple limitations that prohibit usage for 40nm technologies and... » read more