Author's Latest Posts

Efficient Verification Of Mixed-Signal SerDes IP Using UVM
By Cadence - 27 Sep, 2017 - Comments: 0

Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal v... » read more

Modeling Of The Electrical Performance Of The Power And Ground Supply For A PC Microprocessor On A Card
By Cadence - 09 Aug, 2017 - Comments: 0

The electrical characteristics of the power and ground supply of a PC microprocessor packaged in a Ball Grid Array (BGA) package mounted on a card are studied by dynamic electromagnetic field analysis. The effects of decoupling capacitors of different types and at different locations are investigated to achieve the objectives of low power and ground impedance and no or insignificant resonances ... » read more

Choosing The Right Superlinting Technology For Early RTL Code Signoff
By Cadence - 28 Jun, 2017 - Comments: 0

No one can afford to go through weeks of verification only to discover problems in the register- transfer level (RTL) code that might not be functionally wrong, but do not follow established rules for successful implementation. Traditional lint tools have become ineffective in evaluating RTL code for today’s larger, more complex designs. However, superlinting technology, such as the Cadence J... » read more

Save Time And Minimize Errors By Automating Co-Design And Co-Analysis Of Chips, PCBs, And Packages
By Cadence - 07 Jun, 2017 - Comments: 0

Given the complexity of today’s chips, packages, and PCBs, designing each in isolation is no longer judicious. Cross-domain co-design and co-analysis are key to ensuring optimal performance, cost reduction, and faster time to market. Such capabilities are provided by the Cadence Virtuoso System Design Platform, which integrates IC design—including multiple heterogeneous die—into the Alleg... » read more

Choosing The Right Verification Technology For CDC-Clean RTL Signoff
By Cadence - 24 May, 2017 - Comments: 0

Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result... » read more

High-Level Low-Power System Design Optimization
By Cadence - 10 May, 2017 - Comments: 0

High-level decisions have the most impact on power consumption, but the effect of those decisions cannot be known until the hardware is implemented. This paper walks the reader through an industrial high-level low-power design methodology that enables the designer to consider and quantitatively evaluate a broad range of hardware implementations to find the most power-efficient architecture. Thi... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 26 Apr, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSim Parallel Si... » read more

A Program Manager’s Guide to Successful Integrated Circuit Verification
By Cadence - 12 Apr, 2017 - Comments: 0

Accurately monitoring progress on complex integrated circuit (IC) designs has become more difficult as the designs have increased in complexity, leading to surprises from backwards-looking reporting and management processes that do not forewarn coming crises. The Cadence Metric-Driven Verification Methodology provides a more uniform and standardized method of reporting progress towards closure ... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Power-Aware Analysis Solution
By Cadence - 25 Jan, 2017 - Comments: 0

By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flow, and examining what is employed in Cadence Sigrity power and signal simulations using the SPEED2000, PowerSI, Transistor-to-Behavioral Model Conversion (T2BTM), and SystemSI tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also ... » read more

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