Efficient Verification Of Mixed-Signal SerDes IP Using UVM

Lines blur as processors are added into traditional FPGAs, and programmability is added into ASICs.

Goal is to improve quality while reducing time to revenue, but it’s not always so clear-cut.

But working with this architecture has some not-so-obvious pitfalls, and new tools licensing options may be necessary.

So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.

What AI and deep learning are good for, what they’re not good for, and why accuracy sometimes works against these systems.

When does a large amount of data become Big Data, and could system-level verification benefit from it?

Acceleration of advanced processes, skyrocketing complexity and cost, and concerns about IP availability are raising some difficult questions.

Part 1: New opportunities and potential pitfalls in automotive, 5G, connected intelligence and infrastructure as a service in EDA.