System-Level Design
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Pattern-Based Analytics To Estimate And Track Yield Risk Of Designs Down To 7nm

Scoring patterns to identify problems and trends, and to make comparisons between different designs.

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Topological pattern-based methods for analyzing IC physical design complexity and scoring resulting patterns to identify risky patterns have emerged as powerful tools for identifying important trends and comparing different designs. In this paper, previous work is extended to include analysis of layouts designed for the 7nm technology generation. A comparison of pattern complexity trends with respect to previous generations is made. In addition to identifying topological patterns that are unique to a particular design, novel techniques are proposed for scoring those patterns based on potential yield risk factors to find patterns that pose the highest risk.

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