Author's Latest Posts

Accelerating Monte Carlo Analysis At Advanced Nodes
By Cadence - 10 Aug, 2016 - Comments: 0

Advanced-node designs have much larger variation, making it much more difficult to achieve high yields at these processes. But can you really afford to run thousands or even millions of statistical simulations to predict how well your design will meet its specs? Or overdesign to accommodate manufacturing variations? In this paper, we will introduce a fast Monte Carlo analysis technique that del... » read more

Automating Inter-Layer In-Design Checks In Rigid-Flex PCBs
By Cadence - 27 Jul, 2016 - Comments: 0

Flexible PCBs (flex/rigid-flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. As flexible PCB fabrication technology has matured in response to demands for smaller, lighter products, new design challenges have emerged. This paper discusses some of the key challenges to address and also ... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below
By Cadence - 13 Jul, 2016 - Comments: 0

At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

Addressing The Challenges Of Photonic IC Design Via An Integrated Electronic/Photonic Design Automation Environment
By Cadence - 11 May, 2016 - Comments: 0

Photonics—the science and technology of generating, controlling, and detecting light—is transitioning quickly into mainstream electronic designs. Photonic IC (PIC) design does, however, come with some unique challenges in areas including layout, error checking, and circuit modeling. While electronic designers would have expertise in using a traditional electronic design automation (EDA) flo... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 Apr, 2016 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifie... » read more

Improving Emulation Throughput For Multi-Project SoC Designs
By Cadence - 28 Oct, 2015 - Comments: 0

As design sizes grow, so, too, does the verification effort. Indeed, verification has become the biggest challenge in SoC development, representing a majority share of the development cost, both for hardware itself and for verification at the hardware/software interface. And today, it’s not uncommon for companies to have distributed teams working on multiple SoC designs in parallel. In some c... » read more

Property Synthesis Throughout The Design Flow For Application In Formal Verification, Simulation, And Emulation
By Cadence - 23 Sep, 2015 - Comments: 0

This white paper describes the JasperGold Property Synthesis Apps, members of a family of interoperable, application-specific formal verification solutions that addresses verification challenges throughout the design flow. The Apps synthesize both behavioral and structural properties — also known as assertions — for use in formal verification, simulation and emulation. They significantly in... » read more

Gate-Level Simulation Methodology
By Cadence - 26 Aug, 2015 - Comments: 0

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of gate-level simulation (GLS) applications including design for test (DFT) and low- power considerations. As a result, in order to complete the verification requirements on time, it becomes extr... » read more

Formal Verification For Post-Silicon Debug
By Cadence - 08 Jul, 2015 - Comments: 0

Bug escape costs grow considerably with each and every subsequent step in the design flow, to the point of being exorbitantly high once at the silicon level. As a result, these high costs of bug escape are driving customers to embrace formal verification for post-silicon debug and to begin using formal far earlier in the flow for their next design projects. The Cadence JasperGold Verification S... » read more

Interoperable Application-Specific Solutions For Formal Verification
By Cadence - 24 Jun, 2015 - Comments: 1

Historically, formal verification technology has been licensed as a compre- hensive suite of tools that can be used to address a broad range of formal verification applications and problems. Such deployment required a wide range of in-depth skills on the user’s part before the technology could be leveraged by not only first time users, but also experienced ones. New users were often overwhelm... » read more

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