Transparent program status, data-mining and progressive access to details that can impact schedules.
Accurately monitoring progress on complex integrated circuit (IC) designs has become more difficult as the designs have increased in complexity, leading to surprises from backwards-looking reporting and management processes that do not forewarn coming crises. The Cadence Metric-Driven Verification Methodology provides a more uniform and standardized method of reporting progress towards closure in meeting specification requirements. Driven by the vManager Metric-Driven Signoff Platform, the solution provides transparent program status, data-mining capabilities, and progressive access to the details of issues that have potential schedule impact, by providing program managers and oversight officers the information to achieve the desired goal of first-pass success.
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