Transparent program status, data-mining and progressive access to details that can impact schedules.
Accurately monitoring progress on complex integrated circuit (IC) designs has become more difficult as the designs have increased in complexity, leading to surprises from backwards-looking reporting and management processes that do not forewarn coming crises. The Cadence Metric-Driven Verification Methodology provides a more uniform and standardized method of reporting progress towards closure in meeting specification requirements. Driven by the vManager Metric-Driven Signoff Platform, the solution provides transparent program status, data-mining capabilities, and progressive access to the details of issues that have potential schedule impact, by providing program managers and oversight officers the information to achieve the desired goal of first-pass success.
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Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
Semiconductor devices face many hazards before and after manufacturing that can cause them to fail prematurely.
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
Slowdown due to impact on timing, and dependencies between power, thermal and timing that may not be caught by signoff tools.
Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.
Stacking die is garnering more attention, but design flows aren’t fully ready to support it.
Understanding aging factors within a design can help reduce the likelihood of product failures.
How Arm sees its role in emerging segments of tomorrow’s compute challenges.
New data flow, higher switch density and IP integration create issues across the design flow.
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