2023: A Good Year For Semiconductors


Looking back, 2023 has had more than its fair share of surprises, but who were the winners and losers? The good news is that by the end of the year, almost everyone was happy. That is not how we exited 2022, where there was overcapacity, inventories had built up in many parts of the industry, and few sectors — apart from data centers — were seeing much growth. The supposed new leaders we... » read more

Everything, Everywhere, All At Once: Big Data Reimagines Verification Predictability And Efficiency


Big data is a term that has been around for many years. The list of applications for big data are endless, but the process stays the same: capture, process and analyze. With new, enabling verification solutions, big data technologies can improve your verification process efficiency and predict your next chip sign-off. By providing a big data infrastructure, with state-of-the-art technologies... » read more

Manufacturing Bits: May 11


Covid-19 data mining Using machine learning and other technologies, Lawrence Berkeley National Laboratory (Berkeley Lab) has developed a data text-mining tool to help synthesize a growing amount of scientific literature on Covid-19. Each day, some 200 new journal articles are being published on the coronavirus alone, according to Berkeley Lab. Berkeley Lab’s data mining tool, which is liv... » read more

Using Machine Learning To Gain Data Insights


Today’s consumers have little appetite for networks that go down, for electronic devices that fail, and for any kind of digital service that doesn’t deliver as promised every time. Reliability is no longer a nice-to-have. It's  a key feature. The continued scaling of advanced electronics and chip manufacturing technologies, however, makes reliability harder to achieve — even as expectati... » read more

Data-Driven Verification Begins


Semiconductor Engineering sat down to discuss data-driven verification with Yoshi Watanabe, senior software architect at Cadence; Hanan Moller, systems architect at UltraSoC; Mark Conklin, principal verification engineer at Arm; and Hao Chen, senior design engineer at Intel. What follows are excerpts of that conversation, which was conducted in front of a live audience at DVCon. (L-R) Yosh... » read more

Hardware Security Threat Rising


Martin Scott, senior vice president and CTO of Rambus, sat down with Semiconductor Engineering to talk about an increasing problem with security, what's driving it, and why hardware is now part of the growing attack surface. What follows are excerpts of that conversation. SE: With Meltdown and Spectre, the stakes have changed because the focus is not on using hardware to get to software. It'... » read more

System Bits: May 29


Ultra-low-power sensors carrying genetically engineered bacteria to detect gastric bleeding In order to diagnose bleeding in the stomach or other gastrointestinal problems, MIT researchers have built an ingestible sensor equipped with genetically engineered bacteria. [caption id="attachment_24134598" align="alignleft" width="300"] MIT engineers have designed an ingestible sensor equipped with... » read more

Applying Machine Learning To Chips


The race is on to figure out how to apply analytics, data mining and machine learning across a wide swath of market segments and applications, and nowhere is this more evident than in semiconductor design and manufacturing. The key with ML/DL/AI is understanding how devices react to real events and stimuli, and how future devices can be optimized. That requires sifting through an expandi... » read more

Using Data Mining Differently


The semiconductor industry generates a tremendous quantity of data, but until very recently engineers had to sort through it on their own to spot patterns, trends and aberrations. That's beginning to change as chipmakers develop their own solutions or partner with others to effectively mine this data. Adding some structure and automation around all of this data is long overdue. Data mining h... » read more

What’s In The Package?


Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

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