How to simulate multi-core, multi-million-gate designs and still get chips out the door on time.
As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSim Parallel Simulation Engine are eliminating the functional verification bottleneck.
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