A look at the signal integrity methodology requirements necessary to achieve high-quality designs.
By reviewing the classic (or traditional) SI methodology, analyzing high-speed design flow, and examining what is employed in Cadence Sigrity power and signal simulations using the SPEED2000, PowerSI, Transistor-to-Behavioral Model Conversion (T2BTM), and SystemSI tools, this paper explains how a general power-aware SI solution not only should be capable of performing SSN simulations, but also capable of creating and extracting signal and power analysis-required models and running design checks with power-aware constraints. Providing such a complete, or true, “power-aware solution” gives designers the confidence to produce high-quality designs.
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