Author's Latest Posts


Proprietary Vs. Commercial Chiplets


Large chipmakers are focusing on chiplets as the best path forward for integrating more functions into electronic devices. The challenge now is how to pull the rest of the chip industry along, creating a marketplace for third-party chiplets that can be chosen from a menu using specific criteria that can speed time to market, help to control costs, and behave as reliably as chiplets developed in... » read more

Next-Gen Power Integrity Challenges


Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Very Short Reach SerDes In Data Centers


Speed is critical inside of data centers, and the distance that signals have to travel can have a big impact on time to results. But there are a number of variables that need to be considered, including what is an acceptable loss, how much power can be dissipated in a server rack, and what are the various connection options being used. Keivan Javadi Khasraghi, staff technical product manager at... » read more

Making Heterogeneous Integration More Predictable


Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Improving AI Productivity With AI


AI is showing up or proposed for nearly all aspects of chip design, but it also can be used to improve the performance of AI chips and to make engineers more productive earlier in the design process. Matt Graham, product management group director at Cadence, talks with Semiconductor Engineering about the role of AI in identifying patterns that are too complex for the human brain to grasp, how t... » read more

What To Do About Electrostatic Discharge


Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

What Can Go Wrong In Heterogeneous Integration


Experts at the Table: Semiconductor Engineering sat down to discuss heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom IC & PCB Group; and Tony Mastroia... » read more

Total Overlay With Multiple RDLs


As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

DRAM Choices Are Suddenly Much More Complicated


Chipmakers are beginning to incorporate multiple types and flavors of DRAM in the same advanced package, setting the stage for increasingly distributed memory but significantly more complex designs. Despite years of predictions that DRAM would be replaced by other types of memory, it remains an essential component in nearly all computing. Rather than fading away, its footprint is increasing,... » read more

Designing Chips For Outer Space


If designing chips in cars sounds difficult, try designing them for space. There are huge temperature swings, and more radioactive particles than on Earth, which can cause single-event upsets, transients, functional interrupts, and latch-ups. A destructive latch-up can ruin a device, and in space that could transform an expensive piece of hardware into space junk. Ian Land, senior director for ... » read more

← Older posts Newer posts →