Geoff Tate

  (all posts)
Geoff Tate is the founder and CEO of Flex Logix. Tate has more than three decades of experience in technology. He is the former CEO of Rambus, and a current board director at Everspin Technologies. He received his BSc in computer science from the University of Alberta, and an MBA from Harvard Business School.

Author's Latest Posts

High Neural Inferencing Throughput At Batch=1
By Geoff Tate - 06 Dec, 2018 - Comments: 0

Microsoft presented the following slide as part of their Brainwave presentation at Hot Chips this summer: In existing inferencing solutions, high throughput (and high % utilization of the hardware) is possible for large batch sizes: this means that instead of processing say one image at a time, the inferencing engine processes say 10 or 50 images in parallel. This minimizes the number of... » read more

Real-Time Object Recognition At Low Cost/Power/Latency
By Geoff Tate - 01 Nov, 2018 - Comments: 0

Most neural network chips and IP talk about ResNet-50 benchmarks (image classification at 224x224 pixels). But we find that the number one neural network of interest for most customers is real-time object recognition, such as YOLOv3. It's not possible to do comparisons here because nobody shows a YOLOv3 benchmark for their inferencing. But it's very possible to improve on the inferencing per... » read more

Reconfigurable eFPGA For Aerospace Applications
By Geoff Tate - 12 Oct, 2018 - Comments: 0

Market research reports indicate about 10% of all dollar revenue of FPGA chips is for use in aerospace applications, and DARPA/DoD reports indicate about one-third of all dollar volume of ICs purchased by U.S. aerospace are FPGAs. FPGAs clearly are very important for aerospace applications because of a combination of short development time and the long mission life of many aerospace applica... » read more

Flexible, Energy-Efficient Neural Network Processing At 16nm
By Geoff Tate - 06 Sep, 2018 - Comments: 0

At Hot Chips 30, held in August in Silicon Valley, Harvard University (Paul Whatmough, SK Lee, S Xi, U Gupta, L Pentecost, M Donato, HC Hseuh, Professor Brooks and Professor Gu) made a presentation on “SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IOT Devices. ” (Their complete presentation is available now on the Hot Chips website for attendees and will be p... » read more

Sandia Labs’ New Configurable SoC
By Geoff Tate - 02 Aug, 2018 - Comments: 0

At DAC 2018, held in June in San Francisco, Sandia Labs made a public presentation for the first time describing its first SoC using eFPGA, called Dragonfly. This is the first public disclosure by any organization describing its requirements, architecture and use cases for the new technology option of embedded FPGA. John Teifel led the project for Sandia National Laboratories. Sandia has ... » read more

Reconfigurable AI Building Blocks For SoCs And MCUs
By Geoff Tate - 10 Jul, 2018 - Comments: 0

FPGA chips are in use in many AI applications today, including Cloud datacenters. Embedded FPGA (eFPGA) is now becoming used for AI applications as well. Our first public customer doing AI with EFLX eFPGA is Harvard University, who will present a paper at Hot Chips August 20th on Edge AI processing using EFLX: "A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devi... » read more

Architects: How To Get The Most Out Of eFPGA
By Geoff Tate - 07 Jun, 2018 - Comments: 0

At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA. 1. Use as little eFPGA a... » read more

Timing Signoff Methodology For eFPGA
By Geoff Tate - 03 May, 2018 - Comments: 0

An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Introduction To eFPGA Software
By Geoff Tate - 05 Apr, 2018 - Comments: 0

In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software. An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC. The clock(s) for the eFPGA come from the SoC. The configuration of the eFPGA is done by the SoC... » read more

eFPGA: Think Differently & Experiment
By Geoff Tate - 01 Mar, 2018 - Comments: 0

New technologies are never overnight successes and usually develop in new applications. Arm and other embedded processors today are a huge success and pervasive in almost all chips. It took Arm more than five years to win the first five customers. The first applications were not competitive with Intel’s PC dominance but instead filled needs in emerging applications such as mobile phones an... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy