Sandia Labs’ New Configurable SoC

Why the national lab opted for an embedded FPGA.

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At DAC 2018, held in June in San Francisco, Sandia Labs made a public presentation for the first time describing its first SoC using eFPGA, called Dragonfly.

This is the first public disclosure by any organization describing its requirements, architecture and use cases for the new technology option of embedded FPGA.

John Teifel led the project for Sandia National Laboratories. Sandia has its own 180nm CMOS Fab at their Albuquerque facility, and wanted an eFPGA for it to enable a series of SoCs that will be able to be reconfigured to handle multiple applications and to be updated as needed in system.

Sandia’s requirement was that the eFPGA be designed using its standard cells/PDK, have only 6 metal layers (most commercial FPGA chips use many more metal layers), have a building block approach enabling sizes of 4K to 16K LUTs, and have I/O count in the 1000s.

Flex Logix’ XFLX patented, hierarchical interconnect enables dense interconnect with half the metal layers of traditional mesh FPGA interconnects. And XFLX enables Flex Logix to design eFPGA in about 6 months using standard cells while achieving high density.

Even though the eFPGA delivered is in 180nm, it uses the exact same digital architecture (Gen2 EFLX4K) implemented on TSMC28HPC/HPC+, TSMC16FF+/16FFC/12FFC and is now in design for GlobalFoundries 14LPP.

This means Sandia can use the same EFLX Compiler, with GUI Interface, that all of Flex Logix’ other customers use. The only difference is that for Sandia the timing file is based on timing arcs automatically extracted from the Sandia 180nm GDS for its’ process corners.

Flex Logix was able to do the port to Sandia’s process in the target 6 months. And Sandia was able to integrate the first EFLX eFPGA array into their first SoC in 3 months (Dragonfly is just the first SoC they plan to do). The Dragonfly SoC is now in fabrication at Sandia.

Sandia disclosed its block diagram for Dragonfly: Dual ARM processors each with AHB, GPIO and SPI connections to a single EFLX4K eFPGA array on the north side; then with several dual-port SRAMs, serial bus nodes, GPIO and configuration/startup connections on the south side. Even a single EFLX4K has >1000 CMOS inputs/outputs enabling all of this interconnectivity.

Sandia then disclosed some usage cases for the Dragonfly reconfigurable SoC:

  1. Accelerator functions, such as AES: FPGA for many workloads can achieve performance 10-100x greater than a processor (this is why Microsoft is using FPGA accelerators in their data centers for AI and Software Defined Networking). In our Accelerator app note, on our website, we show that AES-128 uses just 1142 LUTs and runs ~100x faster than an ARM Cortex M4. SHA-256 takes 1634 LUTs and runs ~40x faster than an ARM Cortex M4. Many other encryption/decryption algorithms, and there are many, will fit within just 4K LUTs with similar acceleration benefits. Other algorithms can be accelerated as well.
  2. Flexible I/O: there are a wide range of serial I/O protocols with numerous variations. In our Flexible I/O app note, on our website, we show a simple UART needs just 72 LUTs and runs at 30MHz in TSMC40ULP; a 16450 UART uses 302 LUTs running at 25MHz in TSMC40ULP. RTL for SPI and many other serial I/Os are also available from suppliers such as CAST and Silvaco.
  3. Processor-dedicated I/O tasks for when the processors are running different work loads.
  4. Voting Logic when dual-core processors run in lock step: this is a typical operating mode for high reliability applications like Space and Automotive where reliable operation is paramount.

This is the first public disclosure of the usage of an eFPGA in an SoC, but certainly will not be the last. Flex Logix has more than 10 customer chips in silicon, in fab and in design, and there are many more customers doing detailed evaluation. Applications range from Aerospace to Automotive, Networking to Telecommunications/Base Stations, MCUs to Machine Learning.

Next up: Harvard University at HotChips will present a paper on their Flexible Edge DNN design in TSMC16FFC using EFLX eFPGA.



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