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Reconfigurable eFPGA For Aerospace Applications

Flexibility is critical for satellites that may be orbiting for 20 years.


Market research reports indicate about 10% of all dollar revenue of FPGA chips is for use in aerospace applications, and DARPA/DoD reports indicate about one-third of all dollar volume of ICs purchased by U.S. aerospace are FPGAs.

FPGAs clearly are very important for aerospace applications because of a combination of short development time and the long mission life of many aerospace applications. When a satellite is orbiting the earth for 20 years, the mission can change in ways that are unpredictable. An FPGA can be reconfigured to adapt.

Also, FPGAs, like Microsoft has shown in its data center, are excellent at accelerating critical workloads like DSP encryption/decryption, where parallelism can be exploited to outperform processors by 30 to 100X.

But FPGAs can be improved. FPGAs used in aerospace today are are large, heavy and power-hungry due to all the SerDes required to communicate with ASICs/processors. And they are almost all manufactured in Asia. In addition, very few have radiation resistance for space applications. Those that do are extremely expensive.

Embedded FPGA maintains the good features of FPGA while offering solutions for the drawbacks. When integrated on-chip, eFPGA buses can be hundreds of bits wide running at high speeds (GHz in finFET processes), eliminating performance bottlenecks and SerDes power drain. eFPGA on chip is much less expensive than FPGA chips, and integration eliminates bulky/heavy packaging.

Flex Logix designs eFPGA with standard cells, yet achieves performance and density similar to discrete FPGAs because of the interconnect technology, which provides high-bandwidth, high-utilization connectivity using half the area of traditional mesh interconnect used in other FPGAs. Standard cells can be “ported” using our digital architecture to any CMOS process in six to eight months. And if we are given rad-hard standard cells, the resulting eFPGA will be rad-hard by design.

We have been working with U.S. aerospace companies and government organizations for several years now.

Sandia Labs described its Dragonfly SoC, which is now out of fab and working, at DAC in June 2018. We ported our EFLX4K eFPGA core to their proprietary 180nm process made in New Mexico. Below is one of their slides showing some of the use cases for eFPGA in their ASICs.

Dragonfly is out of fab and working. Sandia has a license to build multiple ASICs using eFPGA in various sizes and configurations.

For DARPA, we designed and fabricated a 200K LUT4 eFPGA array in TSMC16FFC. It has been validated over process and temperature to demonstrate the feasibility of very large, very fast (GHz) eFPGA to the Aerospace industry and government. The array is constructed in a 7 x 7 matrix, with two rows of DSP cores and the rest logic cores. DSP and logic can be intermixed in any combination to get the right balance of MACs and LUTs for a given customer’s application. This array is available on evaluation boards for customers, aerospace and commercial, to download their eFPGA designs to verify performance and power on real silicon.

The DARPA and Sandia projects led to an increasing amount of evaluation by government organizations and aerospace companies over the last couple of years. Now there are multiple chips in design, in contract and many more in planning. Some of the applications will use arrays of >100K LUT4s. Most of the chips use multiple, different eFPGA array sizes on the same chip: for example, one block may implement reconfigurable serial I/O; another a reconfigurable memory controller for a DDR PHY; another a reconfigurable accelerator co-processor for the ARM core; and another a reconfigurable encryption/decryption unit.

To address the requirement for U.S. manufacturing, we are now porting our EFLX4K Logic and DSP cores to GlobalFoundries 14LPP/12LP, which is manufactured in Malta, near Albany, in upstate New York State. We also will build a validation chip, as is our standard practice, to validate performance over the full voltage and temperature ranges, and we will offer an evaluation board enabling customers to download their eFPGA designs to run on real silicon to verify performance and power.

Boeing announced earlier this month it has licensed EFLX eFPGA on the GF14LPP process and are in design. More companies, organizations and chips are in design, in contracting and in planning for GF14LPP/12LPP.

Another growing requirement for Aerospace is neural network acceleration for vision and other sensing applications.

Harvard University, at Hot Chips in August 2018, presented a paper where it implemented multiple, flexible Deep Neural Network processors in TSMC16FFC to evaluate their efficiency in area and power.

For neural networks, flexibility is practically a must. The rate of change in algorithms is dramatic, and any silicon that is designed must be expected to need to run neural networks that weren’t invented when the silicon was architected. They selected the EFLX eFPGA to implement a 16K LUT4 array, with 2 Logic cores and 2 DSP cores. They also implemented two other flexible approaches: an ARM Cortex-A53 CPU cluster and cache-coherent datapath accelerators (ACC).

To test the efficiency of the three flexible NN appraoches, representative DNN kernels were executed on all 4 blocks.

Of the flexible DNN engines, the eFPGA array achieved energy efficiency much better than the other two: 4.5x the energy efficiency of CPUs.

Regarding area efficiency, eFPGA was similar to CPU but somewhat less than ACC.

This is an impressive result for eFPGA considering it is not optimized for DNN inference.

On Nov. 1 at the Linley Processor Conference, Flex Logix will announce NMAX for edge neural inferencing: scalable, high performance with very low DRAM bandwidth. NMAX is not an eFPGA, but uses eFPGA and several of our proprietary interconnects. This will give maximum performance at minimum system power for Aerospace and commercial edge applications alike.

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