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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

The Week In Review: Design
By Jesse Allen - 15 Dec, 2017 - Comments: 0

M&A Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys' burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired. STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Envir... » read more

Blog Review: Dec. 13
By Jesse Allen - 13 Dec, 2017 - Comments: 0

Mentor's Sherif Hany notes that pattern matching isn't just for litho hotspots anymore, and is increasingly being used in a wide range of early design phase checks, DRC flows, layout retargeting and fixing and DFM checks. Synopsys' Eric Huang explains why USB cables have gotten so short, even though no length is mentioned in the specification. Cadence's Paul McLellan listens in as Jeremy ... » read more

Power/Performance Bits: Dec. 12
By Jesse Allen - 12 Dec, 2017 - Comments: 0

Sunny days slow 5G 5G networks promise a world of fast wireless data speeds and connected everything.  However, researchers at Embry-Riddle Aeronautical University and King Saud University found that hot, sunny weather could degrade 5G cellular transmissions by more than 15%. The researchers focused on how solar radio emissions would affect the unlicensed 60 GHz bands, part of the millimet... » read more

The Week In Review: Design
By Jesse Allen - 08 Dec, 2017 - Comments: 0

M&A Design services firm Synapse Design acquired the assets of ACEIC Design Technologies, including the engineering team and verification IP. ACEIC, which was based in Bangalore, primarily focused on verification services for wireless 802.11ac MAC IP. This is only the latest expansion move from Synapse. Earlier this year, the company acquired the services companies Tech Vulcan in San Diego... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2017 - Comments: 0

Synopsys' Eric Huang examines electromagnetic interference, the Bit Error Rate in USB 3.2 and how different transfer types handle errors. Mentor's Nitin Bhagwath points out several things that can cause DDR signals to behave badly, from excessive ringing to stubs in the channel. Cadence's Paul McLellan listens in as Oski CEO Vigyan Singhal explains the basics of assertion-based verificati... » read more

Power/Performance Bits: Dec. 5
By Jesse Allen - 05 Dec, 2017 - Comments: 0

Solar jet fuel Researchers at ETH Zurich demonstrated the ability to use solar energy to create the precursor to jet fuel from water and carbon dioxide, a process that could lead to carbon-neutral air travel. The scientists performed 295 consecutive cycles in a 4 kW solar reactor, yielding 700 standard liters of hydrogen and carbon monoxide (syngas), the precursor to kerosene and other liqu... » read more

The Week In Review: Design
By Jesse Allen - 01 Dec, 2017 - Comments: 0

Tools Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors. IP Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup's hardware and software IP works with a CPU or DSP proc... » read more

Power/Performance Bits: Nov. 21
By Jesse Allen - 21 Nov, 2017 - Comments: 0

Greener greenhouses Researchers at the University of California, Santa Cruz are testing greenhouses capable of generating some of their own energy, without hampering plant growth. Greenhouses use electricity to control temperature and power fans, lights, and other monitoring systems. Electricity-generating solar greenhouses utilize Wavelength-Selective Photovoltaic Systems (WSPVs), a novel ... » read more

The Week In Review: Design
By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Blog Review: Nov. 15
By Jesse Allen - 15 Nov, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm. Synopsys' Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin. Mentor's Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing... » read more

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