Blog Review: Nov. 15

Using formal; thermo-mechanical PCB modeling; IoT in manufacturing; exascale computing.

popularity

Cadence’s Paul McLellan shares highlights from the Jasper User Group, including what to do when formal is not converging on a proof and formal in use at Arm.

Synopsys’ Anders Nordstrom explains how formal can verify SoC interconnects and get you from San Jose to Austin.

Mentor’s Jeff Miller argues that intelligent sensors are the basic building block for the IoT, and the market is growing fast.

Ansys’ Michael Kuron and Mike Bak discuss three modeling approaches for the thermo-mechanical analysis of PCBs.

Rambus’ Aharon Etengoff warns of cyber threats against industrial IoT systems, and says one water company has already been compromised.

Arm’s James De Vile examines how readily manufacturing firms are implementing IoT features, both in their products and internal processes.

Lam Research’s Jeff Marks argues for corporate venture activity as a way to promote a vibrant industry.

Intel’s Al Gara says exascale computing is almost here in both the U.S. and China, but node scaling alone won’t do the trick.

Mentor’s Jeurgen Schloeffel checks out the upcoming second edition of the ISO 26262 safety standard, which includes a new section for semiconductor and silicon IP suppliers.

Cadence’s Meera Collier argues that AI will become as ubiquitous as electricity and be part of almost every product, without cannibalizing all the jobs.

Synopsys’ Eric Huang takes a look at how USB Audio Device Class 3.0 saves power, and why not to worry about the loss of 2.5mm jacks.

And don’t miss the latest blogs from the Low Power-High Performance newsletter:

Editor In Chief Ed Sperling finds multiple companies focusing on qubits as the next wave in computing kicks into gear, but problems remain.

Mentor’s Matthew Ballance digs into portable stimulus at the block, subsystem and system levels.

Helic’s Magdy Abadir explains the basic steps in EM crosstalk analysis and post-silicon debug.

Cadence’s Dave Pursley argues that you can’t afford to design silicon for a standard as early as 5G, but you also can’t afford not to.

Synopsys’ Gordon Cooper points to some key factors to consider when choosing an embedded vision system.

Rambus’ Frank Ferro observes that from signal integrity issues to EUV, there are tradeoffs involved with moving to the latest nodes.

Moortec’s Oliver King and Ramsay Allen observe that increased gate density and process variability have made ensuring acceptable chip operating conditions more important.

ANSYS’ Annapoorna Krishnaswamy zeroes in on why power grid design has become a limiting factor for PPA.

Arm’s Brian Fuller notes that everyone agrees there’s a big IoT security problem, but now what?

ClioSoft’s Ranjit Adhikary examines why information gets lost and how you can prevent that from happening while also improving efficiency.

Achronix’s Alok Sanghavi looks at how to continue driving performance gains as the benefits of scaling fall off.



Leave a Reply