The Week In Review: Design

Synopsys finalizes Black Duck buy; ST acquires IDE maker Atollic; electromagnetic-aware layout; verification analytics.


Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys’ burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired.

STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Environment (IDE) for embedded development on Arm-based devices and development boards. Based in Sweden, Atollic was founded in 2003. ST paid $7 million in cash, with approximately $1 million more contingent on certain conditions.

Helic’s VeloceRF RF device synthesis, RaptorX EM modeling and Exalto EM parasitic extraction and signoff tools have been integrated with Synopsys’ Custom Design Platform, creating a solution for electromagnetic-aware layout and analysis of mixed-signal, analog, and RF designs. A GUI within Custom Compiler allows for generation of DRC-clean layouts with VeloceRF. The collaboration also blends parasitics from Synopsys’ StarRC and Helic’s 3D RLCK extraction into a unified netlist for EM analysis.

IC Manage launched a new tool that uses big data technology for near real-time visual analytics and interactive reporting of verification results with web-based access. Envision Verification Analytics is capable of combining results from a mix of verification tools and vendors for regression analytics, bug tracking, and coverage results.

ProPlus Design Solutions and MPI Corporation announced a characterization and modeling solution that integrates ProPlus’ SPICE modeling and noise characterization solution with MPI’s probing technologies. The solution allows MPI probe stations, optimized for the ProPlus 9812DX noise analyzer, to perform automated measurement of DC, CV and noise characteristics.

Sonics added a programmable Sequencer to its ICE-P3 energy processing unit, which enables implementing event-driven control of on-chip and external voltage and frequency resources. Currently, it focuses on two styles of resource communication, control via ARM AMBA write transactions and/or general purpose input/output (GPIO) signaling.

Aldec released new re-configurable FPGA-based accelerators dedicated for executing various types of High Frequency Trading (HFT) strategies. The board uses a Xilinx Virtex UltraScale+ XCVU9P FPGA and connects all critical interfaces like Ethernet, QSFP and PCI Express directly to the FPGA.

Efinix received silicon samples for its first programmable product platform based on its programmable architecture, which the company claims provides a 4X Power-Performance-Area advantage over traditional programmable technologies. The samples were built on SMIC’s 40nm Low Leakage process. Product details will be released in the first quarter of 2018.

QuickLogic teamed up with Mentor to optimize Mentor’s Precision Synthesis software for the QuickLogic ArcticPro architecture used in the company’s eFPGA IP. QuickLogic will distribute it as part of its Aurora development tool suite.

iC-Haus adopted Synopsys’ IC Validator and StarRC products for design signoff of its ASICs for industrial, automotive and medical technology. iC-Haus cited a more than 10X faster extraction signoff using half the CPU resources.

CEVA will integrate Performance-IP’s high-performance L2+ Cache with Memory Tracker Technology in its DSPs. The DSPs target smartphones running applications such as Enhanced Voice Services and multicore homogenous and heterogeneous systems using multiple CEVA cores.

Standards & Certifications
The MIPI Alliance opened access to the MIPI I3C sensor interface specification to all companies. New specifications that implement I3C are planned for 2018, including MIPI I3C Host Controller Interface, MIPI Touch, MIPI Debug for I3C, MIPI DisCo for I3C and MIPI CSI-2 v2.1.

Kilopass’ one-time programmable (OTP) NVM technology achieved a three-lot qualification on GlobalFoundries’ 14nm LPP platform, comprised of separate wafer runs passing stress tests to evaluate the reliability of the memory over time.

Tortuga Logic, which creates tools to identify security vulnerabilities in semiconductor designs, closed $2 million Series Seed financing from Eclipse Ventures to accelerate engineering efforts and expand sales and marketing. The company also named Andrew Dauman vice president of engineering. Formerly, Dauman was vice president of engineering at Synopsys and ran the engineering group at Synplicity.

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