The Week In Review: Design

RISC-V tools; dynamic margining; MIPI CCS; HDMI 2.1; PCIe 5.0 VIP.

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Tools
Imperas debuted its RISC-V Processor Developer Suite, a set of models, a software simulator, and tools to validate, verify, and provide early estimation of timing performance and power consumption for RISC-V processors.

IP
Minima Processor revealed its dynamic-margining subsystem IP for near-threshold voltage design. The startup’s hardware and software IP works with a CPU or DSP processor to enable the device to modify power usage in real time during operation in response to performance needs, process variation or environmental conditions.  The solution includes ultra-wide dynamic voltage and frequency scaling (DVFS), which the company says provides 15-20X lower energy as compared to nominal voltage design. Minima and Arm are partnering to produce a low-power implementation of a Cortex-M3 processor.

Synopsys launched HDMI 2.1 IP with HDCP 2.2 content protection. The package includes controllers, silicon-proven PHYs, verification IP, IP Prototyping Kit, and IP subsystem as well as Linux software drivers. It provides 48 Gbps aggregate bandwidth for uncompressed 8K resolution at 60 Hz refresh rate and includes dynamic HDR and eARC support.

Cadence uncorked verification IP for PCIe 5.0.  The VIP provides a verification plan with measurable objectives linked to the specification features and a test suite, plus protocol-specific interactions between the design, the VIP and the testbench. The VIP is written in C and supports a range of verification platforms, all major simulators, and UVM.

Codasip announced the Bk5-64 processor, its first implementation of the 64-bit RISC-V ISA. The processor includes an LLVM-based software development toolchain with advanced profiling.

Standards
The MIPI Alliance released the MIPI Camera Command Set v1.0 (MIPI CCS v1.0), a new specification which defines a standard set of functionalities for implementing and controlling image sensors, including basic features like resolution, frame rate and exposure time, as well as advanced features like phase detection auto focus (PDAF), single frame HDR or fast bracketing. The specification is offered for use with MIPI Camera Serial Interface 2 v2.0 (MIPI CSI-2 v2.0) and is publicly available.

The HDMI Forum released Version 2.1 of the HDMI specification to support a range of higher video resolutions and refresh rates including 8K60 and 4K120, and resolutions up to 10K. Dynamic HDR formats are also supported, and bandwidth capability is increased up to 48Gbps with a new Ultra High Speed HDMI cable. The specification is available to all HDMI 2.0 adopters.

Si2 is putting together a Special Interest Group to identify areas of concern in the IC design ecosystem. The group will launch an industry-wide survey with the goal of creating a white paper to present an industry consensus on specific ways the industry can manage the rising costs of more complex designs and smaller geometries.

Deals
China Euro Vehicle Technology (CEVT) used Mentor’s Volcano VSA COM Designer network design tool with SystemWeaver information management tools from Systemite AB in designing its next-generation in-vehicle networks. CEVT cited a 50% time reduction in the design and verification of end-solutions.

Numbers
Synopsys released fourth quarter financial results with revenue of $696.6 million for the quarter, up 9.9% from the same quarter last year. On a GAAP basis, there was a $0.80 loss per share for Q4 2017, compared to $0.47 income per share for Q4 2016. Non-GAAP income per share was $0.69, down from $0.77 per share in the same quarter last year. For the entirety of the year, revenue was $2.725 billion, up 12.5% from $2.423 billion in fiscal year 2016. On a GAAP basis, income for the year stood at $0.88 per share, compared to $1.73 per share for 2016. Non-GAAP income for the year was $3.42 per share, up from $3.02 per share last year. Next quarter, Synopsys expects revenues of $740 million – $765 million.

Events
OneSpin returns with another holiday puzzle, this year challenging people to use formal tools to solve what may be the world’s hardest Sudoku grid. The deadline is Jan. 7th.

Artificial Intelligence and Convolution Neural Networks: Dec. 4, 6:30-8:30 p.m. at San Jose State University, San Jose, CA. This panel discussion, hosted by the ESD Alliance, will focus on the systems companies are building to gather data and process it to drive business operations. Jim Hogan will moderate.

Decoding Formal: Dec. 7 in San Jose, CA. This regular gathering highlighting formal verification, hosted by Oski, features talks on the application of formal for two high-performance Ethernet switches plus using formal to explore all corner cases while using highly abstract architectural models for deep analysis of design behavior.

14nm 2.5D/HBM2/SerDes Alliance for High-Performance Networking, Computing, Deep Learning and 5G Infrastructure: Dec. 11 in Tokyo, Japan and Dec. 14 in Shanghai, China. Samsung, ASE Group, eSilicon, Rambus and Northwest Logic will present a seminar featuring a complete FinFET-based supply chain that leverages advanced IP and 2.5D technology.

Reuse 2017: Dec. 14 in Santa Clara, CA. In its second year, this tradeshow and conference focused on the IP community will feature keynotes on dealing with IP theft, the evolution of the IP ecosystem, and semiconductor trends from a foundry perspective.