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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Startup Funding: March 2024
By Jesse Allen - 10 Apr, 2024 - Comments: 0

The challenge of moving data from place to place is increasingly a key concern for chip and system designers, and investors are taking note. Numerous startups developing interconnect technologies received significant backing in March, with approaches spanning chiplet-enabling PHYs, photonic fabrics for disaggregated compute and memory, and telecom transceiver modules. Several new startups la... » read more

Blog Review: April 10
By Jesse Allen - 10 Apr, 2024 - Comments: 0

Cadence's Shyam Sharma looks at the evolution of the LPDDR standard and finds that LPDDR5X is opening new specialized markets for low-power DRAMs beyond the traditional areas of mobile, IoT, and automotive. Siemens' Hossam Sarhan and Dusan Petranovic find that new physical verification approaches are needed to ensure the performance and reliability of superconducting ICs and introduce a hybr... » read more

Research Bits: April 8
By Jesse Allen - 08 Apr, 2024 - Comments: 0

Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

Blog Review: Apr. 3
By Jesse Allen - 03 Apr, 2024 - Comments: 0

Siemens' Keith Felton finds that high bandwidth memory integration poses significant challenges for package designers stemming from its unique architecture and stringent performance requirements. Synopsys' Gervais Fong finds out what's new in the USB4 v2 specification, some of its unique challenges involved in doubling the performance capabilities of the USB wired connection, and an intrigui... » read more

Research Bits: Apr. 2
By Jesse Allen - 02 Apr, 2024 - Comments: 0

Stretchy, sensitive circuits Researchers from Stanford University developed skin-like, stretchable integrated circuits capable of driving a micro-LED screen with a refresh rate of 60 Hz and detecting a braille array that is more sensitive than human fingertips. The stretchable transistors are made from semiconducting carbon nanotubes sandwiched between soft elastic electronic materials. The... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2024 - Comments: 0

Cadence's Steve Brown suggests that multi-die technologies will be a key part of the path toward a faster, more efficient chip ecosystem that can support the compressed development cycles now emerging in the automotive industry. Synopsys' John Swanson, Madhumita Sanyal, and Priyank Shukla point to the role of simulation in ensuring seamless operation in the Ethernet ecosystem though rigorous... » read more

Research Bits: March 26
By Jesse Allen - 26 Mar, 2024 - Comments: 0

Skyrmion switches Researchers from the Agency for Science, Technology and Research (A*STAR) and National University of Singapore harnessed skyrmions to build a switch that has the potential to process data faster while using significantly less energy. Skyrmions are magnetic whirls that form in very thin metal layers and can be efficiently moved between magnetic regions. Using a magnetic tun... » read more

Blog Review: March 20
By Jesse Allen - 20 Mar, 2024 - Comments: 0

Synopsys' Kiran Vittal delves into AI chips, including the expansion of chip design beyond traditional semiconductor companies, adoption of RISC-V, and the use of formal equivalence checking to verify complex AI datapaths. Siemens' Patrick McGoff points to a survey that suggests projects deploying design for manufacturing within a PCB design flow are more likely to be completed on-time, on-q... » read more

Research Bits: Mar. 19
By Jesse Allen - 19 Mar, 2024 - Comments: 0

Superconducting loops Researchers from University of California San Diego and University of California Riverside propose using superconducting loops to store and transmit information in a method similar to the human brain. “Our brains have this remarkable gift of associative memory, which we don't really understand,” said Robert C. Dynes, professor of physics at UC San Diego and preside... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2024 - Comments: 0

Cadence's Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host's CPU to reduce latency and improve overall system performance. Synopsys' John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the ... » read more

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