Blog Review: April 24

HBM for AI; IR drop; digital threads; design data management.


Cadence’s Vatsal Patel notes the factors that make high-bandwidth memory ideal for AI, such as improved bandwidth and area from vertical stacking and power reduction features like data bus inversion.

Synopsys’ Rob van Blommestein points to early power network analysis as a way to ensure that enough power is delivered to each transistor to mitigate potential power-related issues within the chip such as IR drop.

Siemens’ Luke Morris and Stephen Ferguson argue that digital thread engineering and simulation are vital in shaping the next generation of increasingly complex semiconductor devices.

Keysight’s Emily Yan highlights key digital transformation trends that impact semiconductor design data management strategies for both large enterprises and startups and some best practices for improving design data accessibility, simplifying version control, and enhancing design traceability

Arm’s Volodymyr Turanskyy checks out what’s new in LLVM 18, including numerous code generation improvements such as SME and SME2 support, extended Function Multi Versioning, and stack clash protection support.

Ansys’ Susan Coleman and Jennifer Procario take a look at how computational fluid dynamics is being used to help prevent the deterioration of historic Thai murals and improve future art preservation techniques.

The ESD Alliance’s Bob Smith chats with Shiv Sikand of IC Manage about how managing design and IP data improves large-scale IC designs and the continuing adoption of hybrid cloud for design and verification design.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Amkor’s Prasad Dhond anticipates as cars move to a central computing architecture that chiplets will be a logical solution to size and cost challenges.

Synopsys’ Shela Aboud digs into why calculating the breakdown voltage of wide bandgap power devices is crucial.

Lam Research’s Yu De Chen looks at testing different DRAM saddle fin profile shapes without the time and cost of wafer-based development.

ASE’s CP Hung shows how traditional chips are transforming into smaller, well-partitioned chiplets that require chip-to-chip interconnections.

eBeam’s Jan Willis focuses on multi-beam mask writers and curvilinear design as key achievements over the last 15 years.

SEMI’s Margaret Kindling shares a handful of unusual electronics trivia.

Leave a Reply

(Note: This name will be displayed publicly)