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The Week In Review: Design


Tools Synopsys announced the latest version of its VCS functional verification solution, which integrates native fine-grained parallelism (FGP) and additional engine optimizations for simulation on existing x86 CPU server configurations. Aldec released the latest version of its requirements lifecycle management solutions for FPGAs/SoCs, adding certification document templates and review c... » read more

Blog Review: Feb. 1


Synopsys' Anand Thiruvengadam investigates the challenges and tradeoffs that come with different abstraction models and use models in mixed-signal verification. Cadence's Paul McLellan highlights 16 big questions facing autonomous cars, from a presentation by Andreessen-Horowitz's Frank Chen. Mentor's Colin Walls says that when it comes to free stuff, keep an eye out for the real cost. ... » read more

Power/Performance Bits: Jan. 31


Microbial nanowires Microbiologists at the University of Massachusetts Amherst report that they have discovered a new type of microbial nanowire, the protein filaments that bacteria use to make electrical connections with other microbes or minerals. The team was motivated by the potential for improved "green" conducting materials for electronics. According to Derek Lovley, professor of... » read more

The Week In Review: Design


Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

Blog Review: Jan. 25


Synopsys' Anand Thiruvengadam looks at why there's an increased need for mixed-signal verification. Mentor's Craig Armenti argues for incorporating design for reliability into PCB projects. Cadence's Paul McLellan reports from the latest in ESDA's Emerging Companies series about the roots and future of RISC-V. NI's James Kimery shares updates from the 3GPP Workshop on 5G in Vienna. ... » read more

Power/Performance Bits: Jan. 24


Printable circuits with silver nanowires Scientists at Duke University compared the conductivity of films made from different shapes of silver nanostructures and found that electrons move through films made of silver nanowires much easier than films made from other shapes, like nanospheres or microflakes. In fact, electrons flowed so easily through the nanowire films that they could function... » read more

The Week In Review: Design


Legal Back in 2013, Synopsys filed suit against ATopTech for copyright infringement. The courts found in favor of Synopsys and ATopTech was damages were set at a little over $30M. With appeals unsuccessful, ATopTech announced that it has filed a voluntary petition under Chapter 11 of the Bankruptcy Code and has filed a motion to sell its businesses using a stalking horse bidder (an initial b... » read more

Blog Review: Jan. 18


Mentor's Michael White warns that while skipping a node can be appealing, be prepared for the increase in computation requirements. Synopsys' Hezi Saar checks out the benefits of moving to the MIPI I3C standardized sensor interface. Cadence's Paul McLellan highlights a talk by Eric Grosse on approaches to security and the RISC-V architecture. Applied's Mike Chudzik explains the problem... » read more

Power/Performance Bits: Jan. 17


Creating magnets with electricity Researchers at the SLAC National Accelerator Laboratory, Korea Advanced Institute of Science and Technology (KAIST), Korea Institute of Materials Science, Pohang University of Science and Technology, Max Planck Institute, and the University of New South Wales drew magnetic squares in a nonmagnetic material with an electrified pen and then "read" this magneti... » read more

The Week In Review: Design


M&A Synopsys acquired another code analysis company, Forcheck. A privately held software company based in the Netherlands, it provided a static analysis tool for detecting coding defects and anomalies in Fortran applications. Forcheck technology will be integrated into the Coverity tool. Terms of the deal were not disclosed. IP & Specifications Cadence launched verification IP ... » read more

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