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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Startup Funding: May 2023
By Jesse Allen - 07 Jun, 2023 - Comments: 0

Photonic interconnects were an area of activity in May, with two companies raising funds for what could be much faster chip-to-chip and chiplet-to-chiplet links. Microstructured optics and metasurfaces also drew investment, with four companies creating products for a range of applications from flexible LEDs to multi-wavelength spectral imaging. The large language models that power many gener... » read more

Week In Review: Design, Low Power
By Jesse Allen - 02 Jun, 2023 - Comments: 0

Arm debuted its latest platform for mobile computing. Arm Total Compute Solutions 2023 adds the new Immortalis-G720 GPU based on the 5th Generation GPU architecture, which redefines parts of the graphics pipeline to reduce memory bandwidth for the next generation of high geometry games and real-time 3D applications. The company also added two new Mali GPUs. In addition, Arm introduced a cluster... » read more

Blog Review: May 31
By Jesse Allen - 31 May, 2023 - Comments: 0

Cadence's Moshik Rubin looks at how the Portable Test and Stimulus Standard (PSS) is finding new use cases in ATE production test by enabling creation of a rich set of functional test scenarios in a reusable way. Synopsys' LJ Chen and Dana Neustadter check out the latest version of the Universal Flash Storage (UFS) standard, which doubles the data transfer rate of the preceding UFS 3.1 solut... » read more

Blog Review: May 24
By Jesse Allen - 24 May, 2023 - Comments: 0

Siemens' Patrick McGoff finds that designers have not had easy tools to address solderability, leaving a critical part of the manufacturing success of a PCB to the component engineer or the contract manufacturer, and points to manufacturing-driven design as a way to avoid quality issues later. Cadence's Rich Chang finds that effective UPF low-power verification and debug involves more than o... » read more

Research Bits: May 23
By Jesse Allen - 23 May, 2023 - Comments: 0

DNA-based molecular computing Researchers at the University of Minnesota proposed a new method of biocomputing. Trumpet, or Transcriptional RNA Universal Multi-Purpose GatE PlaTform, uses biological enzymes as catalysts for DNA-based molecular computing. Researchers performed logic gate operations in test tubes using DNA molecules. A positive gate connection resulted in a phosphorescent glo... » read more

Blog Review: May 17
By Jesse Allen - 17 May, 2023 - Comments: 0

Synopsys' Dana Neustadter examines the key industries driving Ethernet security, challenges to securing Ethernet networks, and the MACsec protocol that guards against network data breaches by encrypting data traffic between Ethernet-connected devices. Siemens' Stephen Chavez points to the improvements gained from design reuse in PCB design but warns that inefficient processes for managing an... » read more

Research Bits: May 16
By Jesse Allen - 16 May, 2023 - Comments: 0

Germanium-tin transistor Scientists at Forschungszentrum Jülich, CEA-Leti, University of Leeds, Leibniz Institute for High Performance Microelectronics, and RWTH Aachen University fabricated a new type of transistor from a germanium-tin alloy. Charge carriers can move faster in the material than in silicon or germanium, which enables lower voltages in operation. “The germanium–tin syst... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 May, 2023 - Comments: 1

Synopsys acquired Silicon Frontline Technology, a provider of an electrical layout verification solution for mixed-signal and analog designs, large-scale power semiconductor devices, and electrostatic discharge protection networks. "This acquisition enables Synopsys to extend the capabilities of our design analysis portfolio and help build out a system-level electrical analysis platform. We als... » read more

Blog Review: May 10
By Jesse Allen - 10 May, 2023 - Comments: 0

Synopsys' Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA). Cadence's Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation ... » read more

Research Bits: May 10
By Jesse Allen - 10 May, 2023 - Comments: 0

Growing 2D TMDs on chips Researchers from Massachusetts Institute of Technology (MIT), Oak Ridge National Laboratory, and Ericsson Research found a way to “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip, a technique they say could enable denser integrations. The researchers focused on molybdenum disulfide, which is f... » read more

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