Blog Review: May 24

PCB solderability; UPF verification; UCIe; AMBA CHI for chiplets; digital twins.


Siemens’ Patrick McGoff finds that designers have not had easy tools to address solderability, leaving a critical part of the manufacturing success of a PCB to the component engineer or the contract manufacturer, and points to manufacturing-driven design as a way to avoid quality issues later.

Cadence’s Rich Chang finds that effective UPF low-power verification and debug involves more than one language and requires more than one EDA tool to work together for low-power implementation or verification.

Synopsys’ Manuel Mota notes that ensuring the success of a UCIe-based multi-die system goes beyond choosing controller and PHY IP to testing, emulation, and silicon lifecycle management.

Arm’s Francisco Socal outlines AMBA’s approach with Coherent Hub Interface (CHI) Chip to Chip (C2C), an extension to on-chip CHI that is being developed to make CHI suitable for connecting chip(let)-to-chip(let) and how it will complement chiplet standardization efforts like UCIe.

Keysight’s Albert Lee looks at the early history of EDA, and the convergence of software integration, parallel computing, and simulation software to understand the potential impact of digital twins.

Ansys’ Arien Sligar explains how to calculate antenna gain, how to increase it, and why determining the ideal gain depends on how the antenna is being used.

Codasip’s Lauranne Choquin argues that by working on processor customization earlier, both hardware and software architects can collaborate from the beginning of the product development and uncover potential performance gains sooner.

Renesas’ Mohammed Dogar highlights measures the company takes to assure quality and reliability, from design reliability verification to the use of statistical process control techniques to monitor the production process and identify any issues that could arise.

SEMI’s Cassandra Melvin chats with Rebecca Dobson of Cadence about the major design challenges the industry is currently facing and opportunities for design companies in automotive, Industry 4.0, and 5G.

IBM’s Mike Murphy considers potential advantages to the chiplet model, from cost and power to flexibility, and why the company is investing in both UCIe and Bunch of Wires.

Intel’s Larry Stewart dives into distributed computing and the communications libraries that make it possible for developers to write effective parallel and distributed applications.

Memory analyst Jim Handy digs into Infineon’s recently introduced NOR flash chip with an LPDDR interface.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Technology Editor Katherine Derbyshire warns that fabs need to understand their water supply and segregate sources that require different levels of treatment.

Amkor’s SeokHo Na points to a reverse-type LAB where lasers transmit through the stage block from bottom BGA side to bumps.

Coventor’s Pradeep Nanja digs into the performance of finFETs under different metal gate critical dimensions and W etch back profiles.

TEL’s Seiji Nagahara urges the entire mask industry to prepare for the new ecosystem surrounding curvilinear data handling and metrology.

Promex’s Dick Otte lays out the manufacturing and packaging challenges in integrating biological technology with electronics.

SEMI’s Timothy Brosnihan questions Omdia’s Nora Houlihan about whether MEMS and bio-inspired sensors will flourish.

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