Blog Review: May 10

Meeting auto chip requirements; CFD and tsunamis; HLS for AI accelerators; RISC-V customizability.


Synopsys’ Alessandra Nardi and Uyen Tran explain how to meet quality, reliability, functional safety, and security requirements of automotive chips through thorough test programs, path-margin monitoring, and design failure mode and effect analysis (DFMEA).

Cadence’s Veena Parthan explores how computational fluid dynamics can help predict and model the generation, propagation, and mitigation of tsunamis and improve safety of the inhabitants and building clusters around coastal regions.

In a podcast, Siemens’ Spencer Acain and Russell Klein chat about how high-level synthesis can make it possible to quickly and efficiently design purpose-built AI accelerators for a wide range of applications, plus how AI improves on optimization heuristics.

Codasip’s Mike Eftimakis checks out how the customizability of RISC-V enables custom instructions for unique workloads, hardware/software co-optimization, optimized PPA at controlled costs, and improved security and reliability.

Ansys’ Akanksha Soni checks out how 3D-IC technologies enable heterogeneous integration of chips such as logic, memory, sensors, and MEMS in a compact form factor and points to the multiphysics challenges of heat transfer, electromigration, stress and strain, and thermal expansion.

Arm’s Peter Harris introduces the latest updates to the astcenc texture compressor for Adaptive Scalable Texture Compression, the advanced lossy texture compression format for the OpenGL ES and Vulkan graphics APIs.

Renesas’ Kevin P. King looks at how AI and signal processing combine for detection of abnormal vibration in motors, a key indicator of a probable or pending failure.

SEMI’s Timothy Brosnihan chats with Nora Houlihan of Omdia about the impact of the recent semiconductor sector slowdown on the MEMS market, expected growth in MEMS speakers, and butterfly-inspired sensors.

Intel’s Greg Lavender stresses that the ecosystem of devices, providers, hardware, and software needs to come together to enable confidential computing by raising awareness, advancing the technology, and lowering the barriers to adoption.

Plus, check out the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Arteris’ Frank Schirrmeister warns that the chip industry needs more time to get safety and security right.

Synopsys’ Filip Thoen explains why traditional bench-based testing and validation no longer suffice for ECUs.

Siemens EDA’s Lee Harrison looks at how any vulnerability in highly connected vehicles can lead to dangerous scenarios.

Flex Logix’s Jeremy Roberson compares the impact of using megapixel images and larger models.

Infineon’s Sneha Prahalad lays out the difference between how non-migratable and migratable keys are used in TPM.

Rambus’ Bart Stevens shows why security anchored in hardware provides the highest level of protection for automotive.

Riscure’s Marc Witteman cautions that protection against side channel analysis is more challenging for post-quantum crypto than for legacy crypto.

Cadence’s Paul McLellan points to big challenges ahead for EV manufacturers.

Onto’s Keith Best warns that with advanced IC substrates, the opportunities for yield loss are significantly higher than for FOPLP.

Advantest’s Shinji Hioki shows how silicon lifecycle management and machine learning can help predict and optimize device reliability.

DR Yield’s Krista Tropper explains why early detection and analysis of process excursions decreases wafer scraps, prevents yield loss, and saves engineering and manufacturing resources.

proteanTecs’ Nitza Basoco moderates a panel on what’s needed for collaborative design.

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