Author's Latest Posts


Blog Review: Nov. 2


Siemens EDA's Harry Foster examines how successful FPGA projects are in terms of verification effectiveness, finding that only 16% of all FPGA projects were able to achieve no non-trivial bug escapes into production, worse than IC/ASIC in terms of first silicon success. Synopsys' Jamie Boote and The Chertoff Group's David London break down best practice guidance and directives U.S. governmen... » read more

Blog Review: Oct. 26


Synopsys' Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP. Siemens EDA's Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on t... » read more

Research Bits: Oct. 25


Polarization for photonic processor Researchers from the University of Oxford and University of Exeter developed a photonic processor that uses multiple polarization channels, increasing information density. "We all know that the advantage of photonics over electronics is that light is faster and more functional over large bandwidths. So, our aim was to fully harness such advantages of phot... » read more

Blog Review: Oct. 19


Siemens EDA's Harry Foster examines trends related to various aspects of FPGA design and the growing design complexity associated with increasing number of embedded processor cores, asynchronous clock domains, and more safety features. Synopsys' Twan Korthorst and Kenneth Larsen take a broad look at silicon photonics, including the benefits of electronic integration, accelerating the develop... » read more

Research Bits: Oct. 18


Modular AI chip Engineers at the Massachusetts Institute of Technology (MIT), Harvard University, Stanford University, Lawrence Berkeley National Laboratory, Korea Institute of Science and Technology, and Tsinghua University created a modular approach to building stackable, reconfigurable AI chips. The design comprises alternating layers of sensing and processing elements, along with LEDs t... » read more

Week In Review: Design, Low Power


Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

Blog Review: Oct. 12


Synopsys' Richard Solomon, Madhumita Sanyal, and Gary Ruggles take a look at the possibilities that CXL 3.0 can bring to a variety of data-driven applications that demand increasingly higher levels of memory capacity, with higher bandwidth, more security, and lower latency. Siemens EDA's Rich Edelman provides some tips for debugging UVM testbenches, such as how to determine what line changed... » read more

Research Bits: Oct. 10


Disposable water-activated battery Researchers at Empa developed a water-activated disposable paper battery that could be used in low-power, single-use disposable electronics such as smart labels for tracking objects, environmental sensors, and medical diagnostic devices. The battery is made of at least one cell measuring one centimeter squared and consisting of three inks printed onto a re... » read more

Startup Funding: September 2022


The onshoring and buildout of dozens of fabs, many costing tens of billions of dollars, is beginning to spill over into other areas that are critical for chip manufacturing. Materials, in particular, which often gets little attention outside of chip manufacturing, witnessed a big spike in September 2022. In fact, seven materials companies covered in this report made up more than a third of the ... » read more

Blog Review: Oct. 5


Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

← Older posts Newer posts →