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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Power/Performance Bits: Aug. 31
By Jesse Allen - 31 Aug, 2021 - Comments: 0

Securing memory Researchers at Columbia University suggest several ways to make computing more secure without imposing a system performance penalty. The efforts focus on memory security, specifically pointers. "Memory safety has been a problem for nearly 40 years and numerous solutions have been proposed. We believe that memory safety continues to be a problem because it does not distribute... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Aug, 2021 - Comments: 0

The UK's Competition and Markets Authority is raising new challenges for Nvidia's proposed acquisition of Arm, suggesting in a new report that an in-depth Phase 2 investigation into the deal is warranted on competition grounds. Andrea Coscelli, chief executive of the CMA, said, “We’re concerned that Nvidia controlling Arm could create real problems for Nvidia's rivals by limiting their acce... » read more

Blog Review: Aug. 25
By Jesse Allen - 25 Aug, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Power/Performance Bits: Aug. 24
By Jesse Allen - 24 Aug, 2021 - Comments: 0

Low power AI Engineers at the Swiss Center for Electronics and Microtechnology (CSEM) designed an SoC for edge AI applications that can run on solar power or a small battery. The SoC consists of an ASIC chip with RISC-V processor developed at CSEM along with two tightly coupled machine-learning accelerators: one for face detection, for example, and one for classification. The first is a bin... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Blog Review: Aug. 18
By Jesse Allen - 18 Aug, 2021 - Comments: 0

Arm's Charlotte Christopherson explores the possibilities of flexible, non-silicon electronics with the creation of PlasticArm, an ultra-minimalist Cortex-M0-based SoC that, even with just 128 bytes of RAM and 456 bytes of ROM, is twelve times more complex than previous flexible electronics. Cadence's Claire Ying highlights the importance of integrity and data encryption (IDE) technology for... » read more

Power/Performance Bits: Aug. 17
By Jesse Allen - 17 Aug, 2021 - Comments: 0

Digital fiber Researchers at MIT, Harrisburg University of Science and Technology, and Rhode Island School of Design developed a digital fiber that can sense, store, analyze, and infer activity after being sewn into a shirt. "This work presents the first realization of a fabric with the ability to store and process data digitally, adding a new information content dimension to textiles and a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Aug, 2021 - Comments: 0

Mobix Labs finalized its acquisition of Cosemi Technologies, a provider of hybrid active optical cables, optical transceivers, and optical engines. Mobix Labs provides wireless connectivity solutions with CMOS-based mmWave beamformers, antenna solutions, and RF semiconductors. “Our Cosemi acquisition bridges the gap between wireless and wired applications, enabling Mobix Labs to bring a full ... » read more

Blog Review: Aug. 11
By Jesse Allen - 11 Aug, 2021 - Comments: 0

Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

Power/Performance Bits: Aug. 9
By Jesse Allen - 09 Aug, 2021 - Comments: 0

Capacitors in interposers Scientists at Tokyo Institute of Technology developed a 3D functional interposer containing an embedded capacitor. They tout the design as saving package area and reducing wiring length, resulting in less noise and power consumption. The capacitive elements are embedded inside a 300mm silicon piece using permanent adhesive and mold resin. The interconnects between ... » read more

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