Week In Review: Design, Low Power

Intel intends to take Mobileye public in mid-2022 on a US market through an IPO of newly issued stock. The subsidiary, which Intel acquired in 2017, develops SoCs for ADAS and autonomous driving solutions. Mobileye has achieved record revenue year-over-year with 2021 gains expected to be more than 40 percent higher than 2020, highlighting the powerful benefits to both companies of our ongoing partnership,” Intel CEO Pat Gelsinger said. “Amnon [Shashua, Mobileye CEO] and I determined that an IPO provides the best opportunity to build on Mobileye’s track record for innovation and unlock value for shareholders.” Intel will remain the majority shareholder in Mobileye.

Tools
Siemens Digital Industries Software and PDF Solutions are collaborating to make their yield analytics products run together for improved aggregation and analysis of yield data. “To achieve faster yield learning and new product introductions, our customers have been asking for tighter integration between different platforms across the semiconductor product lifecycle, including EDA, manufacturing analytics, and test operations,” said John Kibarian, president, CEO, and co-founder of PDF Solutions.

Global Unichip Corporation (GUC) used Cadence’s digital full flow in development of its ASIC designs for mobile, automotive, AI, and hyperscale computing applications. GUC said it reduced floorplan design time from weeks to days and achieved more than 10% reduced wirelength and 5% better switching power by using the Innovus Implementation System’s mixed-placer automation technology.

Siemens Digital Industries Software’s new mPower solution for power integrity analysis of analog, digital, and mixed-signal IC designs is now certified for Tower Semiconductor’s SBC13 and SBC18 process technologies.

RISC-V
Imperas Software introduced an integrated solution for RISC-V processor verification. ImperasDV provides a reference model-based solution for verification that is compatible with the current UVM SystemVerilog methods for SoC verification. “RISC-V offers SoC develops the design freedoms for a custom processor as a unique solution optimized at the point of use, however this shifts the verification task from the few specialist suppliers to all SoC teams,” said Simon Davidmann, CEO at Imperas. The solution aims to support SoC teams in RISC-V verification and includes a RISC-V golden reference model, integrated test bench components, test suites, and professional support and training.

Imagination Technologies debuted a RISC-V CPU product line. The Catapult CPUs can be configured for performance, efficiency, or balanced profiles and target heterogenous designs for a range of markets. “Heterogeneous architectures are key to providing performance, flexibility and resilience when accelerating an increasingly diverse set of workloads,” said Tim Mamtora, Chief of Innovation at Imagination. Four families comprise the line: dynamic microcontrollers, real-time embedded CPUs, high-performance application CPUs, and functionally safe automotive CPUs.

SiFive uncorked its Essential 6-Series range of RISC-V processor IP to target mid-range application capable and real-time processors. The line includes 64-bit Linux-capable, 64-bit real-time, and 32-bit real-time processors and includes pre-configured product specifications that may be tuned towards applications such as general-purpose embedded, industrial, IoT, high-performance real-time embedded, and automotive applications. The company’s 21G3 Release also introduced improved clock gating and power management to its products, among other product updates.

Fraunhofer IPMS and CAST updated the EMSA5-FS RISC-V processor for on-device AI and ML functionality by porting TensorFlow Lite to the processor and adding Zve extensions for vector math processing. “These additions to the EMSA5-FS Processor core now enable the execution of vector instructions that allow parallel processing of datasets and can consequently improve performance as well as energy efficiency,” said Dr. Andreas Weder, group manager Module Integration at Fraunhofer IPMS. “Our users can now reliably implement Edge AI applications such as gesture recognition or vibration analysis.”

RISC-V International and Linux Foundation partnered to release a free online training course focused on toolchains and compilers for RISC-V. Available on the edX platform, RISC-V Toolchain and Compiler Optimization Techniques introduces the compiler toolchain and concepts of cross-compilation and how to use popular compiler toolchains (both LLVM and GCC) to build RISC-V applications. It also covers debugging toolchain issues and what resources to consult when help is needed.

SEGGER added support for 64-bit RISC-V CPUs, including RV64I, RV64E and RV64GC with floating-point unit to its Embedded Studio for RISC-V. It includes emRun C/C++ runtime and emFloat floating-point libraries, the SEGGER Linker, and the SEGGER Compiler, along with the GNU compiler and linker.

IP
Menta announced an embedded FPGA soft IP offering. The company’s eFPGAs have previously been available as hard IP. The new soft IP eFPGA can be mapped by the end user to any foundry on any standard cell technology node, enabling customers to do the physical implementation in their own environment with their own EDA tool flow. “Menta’s eFPGA soft IP enables customers to integrate eFPGAs in the same way as any other digital IP with lower cost and better control of their SoC/ASIC design,” said Vincent Markus, CEO of Menta.

NextChip selected the Rambus RT-640 Root of Trust and MACsec-IP-160 Protocol Engine to provide hardware-level security for its next-generation Apache6 automotive processor. The Apache6 ADAS SoC combines advanced CPU, GPU, ISP and NPU processors to enable automotive vision and domain/zone controller applications such as AVP. “With Rambus security IP solutions, Apache6 offers state-of-the-art protection of mission-critical data while meeting full ASIL-B compliance,” said Hweihn Chung, CTO at NextChip.

sureCore introduced MiniMiser to reduce the power consumption of register files by over 50% for battery-powered devices. Based on a customized storage element, it builds on sureCore’s SRAM power saving techniques for improved power characteristics even at nominal process voltages. “As wearable devices have more and more AI built in to enrich the user experience and provide product differentiation, more memory will be needed to support the computing demands. Cutting their power use has become increasingly important in the quest to achieve a competitive power budget,” said Paul Wells, sureCore CEO.

True Circuits Inc. (TCI) introduced new synthesizable Precision PLL, micro PLL and micro DLL timing IP covering the latest process nodes back to 28nm. The Precision PLL generates multiple precision clocks supporting any modulation scheme from almost DC to 10GHz for SerDes, processor and DVFS applications. The micro PLL is a small synthesizable general-purpose PLL that multiplies the reference clock by any integer or fractional-N value from 1 to 500K. The micro DLL is a small synthesizable DLL with a master and multiple slaves topology that can support reference frequencies typically in the range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range while providing 9-bit accuracy in slave delay programming.

Arasan Chip Systems uncorked a redesigned second-generation MIPI D-PHY IP for the GlobalFoundries 12nm FinFET process node. The D-PHY IP targets wearables and IoT Display applications with a focus on ultra-low power consumption and area optimization.

Rambus used Avery Design Systems’ HBM3 memory models to verify the new Rambus HBM3 Memory Subsystem. Comprised of an HBM3 PHY and HBM3 Controller, the subsystem is optimized for systems that require a high-bandwidth, low-latency memory solution such as AI/ML training, graphics, and HPC.

IoT
Infineon launched the fifth generation of its capacitive and inductive touch sensing human-machine interface (HMI) technology. Targeting user interfaces in home appliance, industrial, consumer, and IoT products, CAPSENSE enables features such as proximity sensing with improved detection range, gesture detection and directivity, and hover detection for touchscreens. “This new generation of CAPSENSE technology builds on our established leadership with an all-new ratiometric and differential sensing architecture. It provides improved noise immunity, and a robust and reliable HMI solution to perform even in the harshest environments with extreme electrical noises, and under extreme weather and temperature,” said Steve Tateosian, Vice President of IoT Compute and Wireless Business Unit of Infineon.

Photonics & quantum
The Intel Research Center for Integrated Photonics for Data Center Interconnects opened. The center’s mission is to accelerate optical input/output (I/O) technology innovation in performance scaling and integration with a specific focus on photonics technology and devices, CMOS circuits and link architecture, and package integration and fiber coupling. Initial projects come from seven US universities and include quantum dot lasers on silicon, optical transceivers, silicon photonic packaging, optical switching, and microring resonator modulators.

IonQ plans to use barium ions as qubits in its quantum computing systems. The company said that using barium should enable lower error rates, higher gate fidelity, and better state detection, as well as more reliable hardware with better uptime and easier networking of multiple quantum processing units. “We believe the advanced architectures enabled by barium qubits will be even more powerful and more scalable than the systems we have been able to build so far, opening the door to broader applications of quantum computing,” said Peter Chapman, president and CEO of IonQ.