Blog Review: Dec. 8

Design and runtime power introspection; counterfeit chips coming; Python and the UVM factory; Samsung’s fab roadmap.


Arm’s Shidhartha Das introduces a method to achieve fast yet accurate power modelling for both design and runtime power introspection within the same unified framework using machine learning and data science approaches.

Synopsys’ Mike Borza warns that the semiconductor industry is facing a flood of counterfeit chips and why being aware of different types of semiconductor scams and tackling the problem at the design phase can help beat the practice.

Siemens EDA’s Ray Salemi continues digging into to using Python for verification with a look at how pyuvm implements the UVM factory as it is described in the specification, removing elements that complicated the factory because of SystemVerilog typing.

Cadence’s Paul McLellan checks out Samsung Foundry’s fab construction roadmap, its strategy for moving processes between fabs, and how it plans to expand capacity 1.7 times by 2026.

Ansys’ Susan Coleman finds out how electromagnetic simulation software is being used in the classroom to engage students and add concrete significance and real-world applicability to an otherwise very abstract subject.

Coventor’s Tae Yeon Oh explores how chemical mechanical planarization (CMP) can create diverse and unexpected topologies in patterned wafers with different layout densities, not only locally but globally across the entire wafer.

The ESD Alliance’s Bob Smith chats with Chris Browy of Avery Design Systems about how an engineer verifies and ensures the compliance of new chip designs with emerging standards when there is no proven system platform yet to support those standards.

Lam Research’s Tim Archer argues that increasing the diversity of the semiconductor industry’s talent pipeline today will dramatically improve the ability to drive new semiconductor breakthroughs in the future.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Rambus’ Bart Stevens zeroes in on different levels of data security and how they are implemented and maintained.

Flex Logix’s Andy Jaros examines different possibilities in the processor subsystem.

Siemens EDA’s Andy Gothard warns that with added connectivity comes a higher risk of attack.

Xilinx’s Brendan Farley shines a light on optimizing cost, power, and performance to ensure the second wave of 5G is a success.

Synopsys’ Fergus Casey and Srini Krishnaswami dig into fusing high-performance processor IP cores with new state-of-the-art safety concepts.

Tortuga Logic’s Jason Oberg points to progress in securing the DoD’s supply chain.

ClioSoft’s Tom Anderson explains why functional correctness, robustness, and readability of IP are vital for high-quality, reusable designs.

Cadence’s Paul McLellan concludes that increasing heterogeneous integration means greater need for system-level analysis.

Onto Innovation’s Johnny Dai describes the benefits of using picosecond ultrasonics for RF process monitoring.

CyberOptics’ Charlie Zhu looks at how to overcome variability in the appearance of corner fill.

Synopsys’ Tomer Morad demonstrates how to monitor system metrics and tune key parameters for optimal performance.

Advantest’s Dave Armstrong and Altanova’s Don Thompson examine why requirements for high-speed I/O test are becoming daunting.

Siemens EDA’s Geir Eide points to reductions in test time with bus-based packetized test delivery.

KLA’s Ben Tsai explores the motivations and challenges for engineers and students across five key regions.

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