Success Stories For Packetized Scan Data

Reductions in test time with bus-based packetized test delivery.


Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The calculation of whether (or when) to adopt new technology includes consideration of the pressures of DFT today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferation of identical cores and tiled designs. The challenges of tomorrow—re-use of high-speed IOs for scan test, testing 3D ICs, and increased bandwidth for non-scan test­—should also be considered.

We have made the case that adopting the new method of delivering scan data as packets on a bus-based network is both easy and important to address DFT challenges of today and tomorrow. Many of the leading semiconductor companies agree and have already implemented the packetized test technology.

Adopters of Siemens’ packetized test, Tessent Streaming Scan Network, have now completed SoC designs and are sharing their stories. Their experiences reveal that Tessent Streaming Scan Network (SSN) offers good automation, compatibility with existing DFT and design flows, a common architecture for all design types, and solid field support. Specific benefits of SSN include cutting DFT development time in half, easing routing and timing closure, and reducing test time and test data by up to 4X.

You can watch presentations by engineers from Broadcom and Intel that were given at the 2021 International Test Conference online.

Broadcom case study

Broadcom Central Engineering designs CPUs; some are targeted to very low-power applications, others to high-performance applications. They typically have multiple voltage domains, 1-3 GHz frequencies, and many instantiated cores. Challenges include low-power test, high-speed designs, and managing test cost. They were asked to implement a scalable test solution for homogenous multi-core high-speed CPU blocks.

Broadcom implemented SSN on a design with 12 identical CPUs, running at over 2.5GHz. They found that testing the identical cores with SSN reduced overall test time by 15%. There was also a significant power benefit; their Shmoo plot showed a 30mV difference between SSN vs. EDT when testing 12 cores in parallel. This is possible with SSN, because shift and capture is done independently across the cores that are tested simultaneously, as shown in figure 1. With SSN, there was no difference in power whether 1 or 12 cores were tested at the same time. Finally, using SSN, they were able to run shift at twice the frequency (2X test time reduction).

Fig. 1: Independent capture reduces test time and allows for a larger number of cores to be tested in parallel without exceeding the power budget.

Watch Srinu Alampally, Master Engineer at Broadcom, explain how they implemented SSN and share the silicon results on a high-speed multi-CPU design in his ITC presentation, Enhancing test on 3GHz designs with SSN.

Intel case study

At the 2020 ITC, Intel compared the SSN method to their traditional pin-mux approach and found a 43% reduction in test data volume and a 43% reduction of test cycles. Implementation and test retargeting tasks were between 10x-20x faster.

At ITC 2021, Intel’s Devices Development Group described their SSN implementation on a multi-die design, in which different die using different test fabrics chare the same IO. Two of the die used SSN and the other two used a custom test fabric. This approach allows them to phase in SSN over time. According to their presentation, the implementation was straightforward, requiring no more effort than their custom fabrics. Setting up the IJTAG requirements took a little more time because it was new to them, but they found the ICL (Instrument Connectivity Language) extract to be a very efficient form of validation. They saw over 2X efficiency gains with pattern retargeting and testing multiple cores in parallel. SSN is able to automatically tune the bandwidth, as shown in figure 2. Each bar represents cores tested simultaneously. The total test time depends on the core with the highest number of cycles. SSN automatically directs more test resources to the cores that need more data, resulting in a scenario shown on the right side.

Fig. 2: SSN reduces test time by allocating more bandwidth to the cores that require more test data.

Watch Dave Dehnert, Principal Engineer at Intel, describe his group’s experience with SSN in his ITC presentation, SSN Implementation on a large multi-die SoC.

Overview of packetized scan test

Unlike the traditional approach to delivering scan test data to cores in which each core requires a dedicated connection to chip-level pins, SSN delivers scan data as packets across a shared bus (figure 3). This creates a very efficient and tunable system. Designers do not need to allocate a fixed number of scan channels for each core or worry about the potential for routing congestion.

Fig. 3: The Streaming Scan Network architecture. The blue line is the high-speed bus that carries the scan data packets in and out of each block. The small boxes are the hosts, and the small blue lines are locally generated DFT signals. The green line represents configuration via IJTAG.

SSN delivers scan test data across a uniform network that is connected to all cores or blocks in a design. The data that is shifted in and out of the chip does not look like conventional scan test data but is organized in packets and translated into more conventional-looking scan data at each core.

With SSN, test controllers are local; core-level host nodes generate the DFT signals locally, ensure that the right data is picked up from the bus and sent to scan inputs of the core and that the output data is placed back onto the bus. Each node knows what to do and when to do it based on a simple configuration step leveraging IJTAG (IEEE 1687) infrastructure.


The Streaming Scan Network is the first commercial full-flow implementation of packetized scan test. Since its introduction, the industry has adopted this technology faster than any other comparable transformative DFT technology, including embedded deterministic test (EDT).

Additional resources:
Technical paper: Streaming Scan Network: A No-Compromise Approach to DFT

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