Author's Latest Posts


Blog Review: Feb. 4


Siemens' Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Cadence's Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability mo... » read more

Research Bits: Feb. 3


Artificial synapse Researchers from Ulsan National Institute of Science and Technology (UNIST) designed a biodegradable, energy efficient artificial synapse that uses a layered structure made from naturally-derived polymers that break down naturally within 16 days in soil. "The device is built like a tiny sandwich, with ion-active layers separated by an ion-binding layer made from cellulose... » read more

Blog Review: Jan. 28


Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

Research Bits: Jan. 27


Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

Blog Review: Jan. 21


Keysight's Armando Valim considers the impact of AI on the memory market as AI infrastructure pressure widens the gap between high-performance memory and lower-margin consumer memory and SSD, forcing manufacturers to make strategic decisions and define which markets to serve. Cadence's Reela Samuel breaks down the major 3D-IC packaging methods used today, from wafer stacking flows to hybrid ... » read more

Research Bits: Jan. 20


ALD for Ru wiring Researchers from Ulsan National Institute of Science and Technology (UNIST), Hongik University, and Tanaka Precious Metal Technologies developed an atomic layer deposition (ALD) process for creating chip interconnects using a ruthenium (Ru) precursor with a thermal stability up to 400 °C. The high-temperature ALD process can produce dense, high-quality Ru films without deg... » read more

Startup Funding: Q4 2025


The promise of AI dominated the last quarter of 2025. Investors were eager to claim stakes in both brand-new startups and more established companies developing AI-specific hardware, primarily for data centers, with over $1 billion alone flowing into the sector. The largest round of the quarter went to a new entrant aiming to fundamentally change how AI compute is performed, while two in-memory ... » read more

Blog Review: Jan. 14


Arm's Paul Black demonstrates how lightweight LLVM sanitizers help detect undefined behavior, improve code quality, and expose hidden bugs in embedded C and C++ projects, with a focus on two sanitizers that can catch issues such as unsigned signed shift overflows, array overflows, and stack corruption. Imagination's Alex Pim provides an overview of LLM inference acceleration for mobile and e... » read more

Research Bits: Jan. 12


Wafer-scale two-photon lithography Researchers from Lawrence Livermore National Laboratory (LLNL) and Stanford University demonstrated a two-photon lithography (TPL) platform for wafer-scale manufacturing. The TPL platform uses large arrays of metalenses to split a femtosecond laser into more than 120,000 coordinated focal spots that write simultaneously across centimeter-scale areas. The a... » read more

Blog Review: Jan. 7


Cadence's Reela Samuel presents an overview of through-silicon vias, including structure, pitch, and electrical behavior, key layout rules such as keep-out zones and stress constraints, and how TSV parasitics influence bandwidth, latency, and system-level performance. Siemens' Andras Vass-Varnai identifies five thermal trends to watch and how they’ll reshape design and packaging workflows ... » read more

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