Blog Review: November 15

Bringing up USB4 links; TCAD improves DTCO; electrical/electronic co-design for PCBs; metalenses; ruthenium metal lines.


Cadence’s Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4.

Synopsys’ Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models.

Siemens’ Stephen Chavez suggests an electrical/electronic co-design approach to enable critical information such as connector part numbers and pin connectivity to be easily shared between PCB engineers and colleagues.

Ansys’ Sanjay Gangadhara introduces metalenses, current fabrication methods, and why they need multiscale, multiphysics simulation that can provide an accurate assessment of both the lens performance across a wide range of apertures and the performance of the metalens inside of a larger optical system.

Lam Research’s Daebin Yim suggests ruthenium as a potential metal line replacement for copper while maintaining the ability to satisfy electromagnetic reliability requirements.

Renesas’ Sree Amirapu notes that while Wi-Fi has been the most popular choice in the IoT world, this is changing with the huge strides made in cellular networks and finds that the type of network connection to use depends on several factors.

Advantest’s Kevin Yan and Daniel Sun find that ultra-wideband (UWB) devices present significant test challenges related to the high RF frequencies at which UWB operates, the ultrawide bandwidths of UWB’s multiple channels, and the technology’s complex modulation schemes.

Codasip’s Roddy Urquhart looks at various methods that are commonly used to address processor integrity and how effective they are at dealing with common memory-related vulnerabilities.

Keysight’s Emily Yan introduces an updated recentering process for semiconductor device modeling to help keep model libraries up with new process targets as process specifications mature continually throughout their lifecycle.

SEMI’s Serena Brischetto chats with Imec’s Lars-Ake Ragnarsson about what makes sustainability so challenging for the semiconductor and electronics industry and the importance of collaboration.

Arm’s Sue Wu provides a tutorial on creating a basic TrustZone example for the Armv8-M processor with Security Extension by using Arm DS and Arm GNU toolchain.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Fraunhofer IIS/EAS’ Jens Michael Warmuth warns that simply improving the failure rate is not enough for today’s electronics requirements.

Arm’s Roberto Lopez Mendez digs into techniques for reducing the precision of weights, biases, and activations to enable real-time edge inference.

Cadence’s Hassan Moezzi makes the case for improving data center planning and operational lifecycle management with digital twins.

Rambus’ Tim Messegee looks at how the third generation of HBM boosts bandwidth while improving power efficiency and memory access.

Siemens EDA’s Qazi Faheem Ahmed shows how dealing with power at each stage of design can help find and fix issues faster.

Keysight’s Mike Wager explores the financial impact of adopting AI-augmented test automation.

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