Blog Review: Dec. 6

Verification cost and generative AI; RISC-V growth factors; FPGA/PCB co-design; MOM, MIM, and MOS.


Cadence’s Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost.

Synopsys’ Kiran Vittal considers the driving factors behind RISC-V’s growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers.

Siemens’ Stephen Chavez notes that FPGA/PCB co-design and optimization can enable fewer net line crossovers, reduced layers, fewer signal integrity issues, shortened traces, and reduced number of vias used.

Ansys’ Akanksha Soni takes a look at the differences between three common types of analog IC capacitors: metal-oxide-metal, metal-insulator-metal, and metal-oxide-semiconductor capacitors.

Renesas’ Jacques Bittar explores the implementation challenges of building autonomous driving and ADAS central computing solutions and why approaches that seem reasonable in early development phases might not be compatible in a production context.

Arm’s Jiaming Guo shows how to profile firmware with Performance Monitor Unit (PMU) in Armv8-A CPU and provides a PMU library as a reference implementation.

Keysight’s Alan Wadsworth explains the differences between auto, seamless, and fixed measurement ranging in source/measure units and when each works best.

The ESD Alliance’s Bob Smith chats with Real Intent’s Prakash Narain about building the company and advice for engineers wanting to transition to management or entrepreneurship.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey reminisces about working in an industry during its infancy that offered both amazing experiences and challenges.

Keysight’s Ben Miller lays out how semiconductor chiplet technology will extend the Moore’s Law benefits of performance and cost while reducing barriers to entry.

Expedera’s Pat Donnelly looks at the generative AI model that is a critical test for NPU design.

Siemens EDA’s John Ferguson points to the persistent challenge of using multi-physics to boost 3D-IC performance.

Synopsys’ Jim Schultz explains how increasing density makes congestion a challenge for both cities and chips.

Movellus’ Barry Pangrle considers the use of AI in semiconductor design and its impact on startups.

Arteris’ Frank Schirrmeister zeroes in on trends shaping chip design and what might be in store next year.

Cadence’s Reela Samuel finds that standardized approaches will be needed to ensure that all chiplets work seamlessly together as a unified system.

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