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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Nov. 4
By Jesse Allen - 04 Nov, 2020 - Comments: 0

Arm's Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint. Mentor's Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try. ... » read more

Power/Performance Bits: Nov. 3
By Jesse Allen - 03 Nov, 2020 - Comments: 0

Wirelessly charging multiple devices Researchers from ITMO University developed a metamaterial that can be used to turn surfaces into wireless charging areas for multiple devices from different manufacturers with different power transfer standards. "There are various wireless power transfer standards with different frequencies, so you can't just use a charger by any manufacturer," said Poli... » read more

Startup Funding: October 2020
By Jesse Allen - 02 Nov, 2020 - Comments: 0

October 2020 was a big month for startups across the automotive space, with sizeable funding all around. Three startups based out of China brought in over $100M apiece for ADAS and autonomous driving, and a fourth U.S.-based startup saw $125M investment for simulating and testing autonomous driving systems. Two electric vehicle manufacturers also received $100M+ rounds. Collectively, the auto c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 30 Oct, 2020 - Comments: 0

M&A AMD will acquire Xilinx for $35 billion in an all-stock deal. "Joining together with AMD will help accelerate growth in our data center business and enable us to pursue a broader customer base across more markets,” said Victor Peng, Xilinx president and CEO. The deal is expected to close by the end of 2021. The acquisition of the programmable logic giant will leave only a few purepla... » read more

Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2020 - Comments: 0

Synopsys' Jacob Wilson provides some tips for how to prepare for the upcoming ISO SAE 21434 cybersecurity standard for road vehicles, starting with a security plan and understanding of risk levels. Cadence's Paul McLellan checks out Arm's first face-to-face wafer-bonded design, why it might be desirable, and some important aspects of how the proof-of-concept was developed. In a video, Men... » read more

Power/Performance Bits: Oct. 27
By Jesse Allen - 27 Oct, 2020 - Comments: 0

Room-temp superconductivity Researchers at the University of Rochester, University of Nevada Las Vegas, and Intel created a material with superconducting properties at room temperature, the first time this has been observed. The researchers combined hydrogen with carbon and sulfur to photochemically synthesize simple organic-derived carbonaceous sulfur hydride in a diamond anvil cell, which... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Oct, 2020 - Comments: 0

M&A Microchip Technology acquired LegUp Computing, a provider of a high-level synthesis compiler that automatically generates high-performance FPGA hardware from software. The LegUp HLS tool will be used alongside Microchip’s VectorBlox Accelerator Software Design kit and VectorBlox Neural Networking IP generator to provide a complete front-end solution stack for C/C++ algorithm develope... » read more

Blog Review: Oct. 21
By Jesse Allen - 21 Oct, 2020 - Comments: 0

Rambus' Frank Ferro and IDC's Shane Rau compare the evolution of HBM and GDDR6, as well as the design tradeoffs and challenges of the two memory types. Mentor's Neil Johnson compares unit testing and formal property checking as first steps for verifying low-level RTL functionality. Synopsys' Patrick Carey considers the competing demands of delivering a product as soon as possible and maki... » read more

Power/Performance Bits: Oct. 20
By Jesse Allen - 20 Oct, 2020 - Comments: 0

Benchmarking quantum layout synthesis Computer scientists at the University of California Los Angeles found that current compilers for quantum computers are inhibiting optimal performance and argue that better quantum compilation design could help improve computation speeds up to 45 times. The team designed a family of benchmark quantum circuits with known optimal depths or sizes, which cou... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Oct, 2020 - Comments: 0

Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

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