Blog Review: Nov. 4

Improving ML on mobile; formal property checking; AI hardware; photonics flows.


Arm’s Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint.

Mentor’s Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try.

Cadence’s Paul McLellan shares some highlights from the recent Linley Fall Processor Conference on the slowing of Moore’s Law and key trends in AI acceleration in both the data center and at the edge.

Synopsys’ Arun Venkatachar looks at why IBM Research and Synopsys are collaborating to build AI-focused hardware and the progress that has already been made.

Ansys’ Rich Goldman and Peter Hallschmid consider the current state of photonics design with more sophisticated electronic-photonic flows and DFM capabilities, plus the major application areas seeing growing use of photonics.

Memory analyst Jim Handy digs into the history of flash memory and how the invention of the charge trap cell brought NAND to where it is today.

In a blog for SEMI, Walt Custer of Custer Consulting finds reason to be optimistic in the IMF’s growth predictions, a recovery of the manufacturing sector, and the seasonal upturn for electronics.

Nvidia’s Ned Finkle listens in on how industry can help speed government agency adoption of AI and why more education, access to data and computing resources, funding, and research are necessary

Intel’s Mario Romao points to some of the challenges for using AI to address global public health and how the need for lots of data to power machine learning models can coexist with protecting personal data privacy.

And don’t miss the blogs featured in last week’s Systems & Design newsletter:

Technology Editor Brian Bailey argues that without a good EDA flow, China’s semiconductor investment is at risk and while its commercial EDA ventures have not been successful, it’s highly likely that work continues behind the scenes.

Cadence’s Frank Schirrmeister observes that industrial process, consumer devices, and aerospace/defense are generating massive amounts of data every day, but where that data is stored and processed is changing.

Synopsys’ Avinash Palepu, Namrata Shekhar and Paula Neeley warn that automatically determining the right verification strategy based on the design characteristics may present challenges.

Mentor’s Ben Whitehead explains how to ensure that the latency, power, and performance of computational storage devices are deterministically analyzed before silicon.

Codasip’s Roddy Urquhart sketches out the complex real-time requirements, multiple privilege modes, and other factors that point to what type of operating system an embedded system needs.

Synopsys’ Shivakumar Chonnad, Radu Iacob, and Vladimir Litovtchenko explain how to stop faults from propagating through coupling factors or cascading from one element to another.

Coventor’s QingPeng Wang illustrates how SEMulator3D can be used to study micro loading and manufacturing variability in an advanced DRAM process that exhibits a wiggling AA profile.

Synopsys’ Robert Ruiz explains how using high-speed PCIe or USB interfaces as scan ports can enhance test performance and allow testing in the field.

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