tag: formal property checking

Verification In Crisis
By Ashish Darbari - 25 Apr, 2024 - Comments: 0

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been improving overall, as has the complexity of designs. For ASICs, 74% of the designs surveyed in the recent Wilson Research Group/Siemens EDA report have one or more processor cores, 52% have two or mor... » read more

Blog Review: Nov. 4
By Jesse Allen - 04 Nov, 2020 - Comments: 0

Arm's Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint. Mentor's Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try. ... » read more

Formal Verification Comes Of Age
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler Formal verification technology, also known as formal property checking, has been in existence since the early 1990s. Still, it’s only in the past five years that it has made big strides in the last five years in terms of the capacity of the technology to handle bigger pieces of a design, leveraging advancements in computing as well as improvements to the algor... » read more

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