Week In Review: Design, Low Power

Microchip buys HLS provider LegUp; new edge inference chip; NN accelerator IP; power electronics virtual prototyping.


Microchip Technology acquired LegUp Computing, a provider of a high-level synthesis compiler that automatically generates high-performance FPGA hardware from software. The LegUp HLS tool will be used alongside Microchip’s VectorBlox Accelerator Software Design kit and VectorBlox Neural Networking IP generator to provide a complete front-end solution stack for C/C++ algorithm developers who want to work with PolarFire FPGA and PolarFire SoC devices without having to understand the underlying RTL development flows. Based in Toronto, Canada, LegUp was founded in 2015 based on research from the University of Toronto. Terms of the deal were not disclosed.

Consulting and business services company Wipro will acquire design services company Eximius Design. Eximius provides ASIC, FPGA, and SoC design and verification for a range of markets including cloud, consumer, and automotive. Eximius’ offerings and solutions will be consolidated as a part of Wipro’s EngineeringNXT framework. Based in Jan Jose, Calif., Eximius was founded in 2013. The deal is expected to close by the end of the year; terms were not disclosed.

POET Technologies and Sanan IC are forming a joint venture, Super Photonics Xiamen, to assemble, test, package and sell optical engines for transceiver module manufacturers. Sanan IC is contributing cash and manufacturing know-how, while POET is providing intellectual property and design know-how. Super Photonics will be based in Xiamen, China.

Chinese regulators could throw a wrench into Nvidia’s acquisition of Arm, Bloomberg reports. Several technology companies in the country have expressed concerns and are lobbying either for a rejection of the deal or conditions that will ensure access to Arm technology, according to Bloomberg’s sources. Two years ago, Qualcomm halted its proposed acquisition of NXP after failing to get approval from Chinese regulators.

Arm unveiled its latest AL/ML-focused IP, the Ethos-U65 microNPU (Neural Processing Unit). Ethos-U65 maintains the power efficiency of the Arm Ethos-U55 but targets higher performance workloads as a neural network accelerator for the Cortex-A, Cortex-R, and Neoverse processor families. The Ethos-U65 provides two different configurations of 256 and 512 MACs/cycle, and it includes a dual AXI to deliver better bandwidth for weight bound networks.

Flex Logix unveiled its InferX X1 AI inference chip for edge devices. It accelerates performance of neural network models such as object detection and recognition for a range of applications. The InferX X1 has 64 1D TPUs that can be configured in series or in parallel to implement a wide range of tensor operations, a silicon area of 54mm2, and provides high MAC utilization up to 70% for large models/images. The InferX Compiler takes models in TensorFlow Lite or ONNX to program the InferX X1.

IBM Research’s AI Hardware Center is beginning some new partnerships and making results of its efforts available. Red Hat will build compatibility between IBM Digital AI Cores and Red Hat OpenShift, an enterprise Kubernetes platform, to enable AI hardware accelerator deployment across hybrid cloud infrastructure. Synopsys will serve as the lead EDA partner for the AI Hardware Center and is working on implementing technologies developed at the Center, with commercialization in the near future.

As part of developing analog AI that combines storage and compute, IBM Research is releasing its Analog Hardware Acceleration Kit as an open source Python toolkit for testing the possibilities of using in-memory computing devices in the context of AI. The kit provides PyTorch integration and an analog devices simulator.

Finally, IBM and NY Creates are investing in a new cleanroom facility that will focus on advanced packaging with fine pitch laminate technology, implementation of silicon bridges, and full 3D integration. The facility will be on the campus of SUNY-Poly in Albany, New York.

Synopsys announced the latest version of its IC Validator physical verification solution, which includes new elastic CPU management technology for compute savings in physical signoff. It also includes faster LVS technology and machine-learning driven root cause analysis to automatically identify critical DRC issues.

Aldec added PYNQ Python Productivity for Zynq from Xilinx to its TySOM family of Xilinx Zynq SoC based boards and its TySOM Embedded Development Kit. PYNQ is an open source platform that abstracts the details of programmable logic, allowing software engineers to develop applications with reduced reliance on support from hardware engineers and speeding development of rapid prototypes.

Synopsys launched a new virtual prototyping solution for power electronics system design. SaberEXP provides simulation convergence and higher productivity for early power component design, such as power converter and motor drive, along with an export flow into high fidelity large system design using Synopsys’ SaberRD. It includes a general-purpose high-abstraction model library, a high-speed mixed mode solver to verify the stability of switched mode power supplies, and parametric and statistical design capabilities.

Arm and Mentor are teaming up on a RTL Verification Design Review service, which will provide access to Mentor functional verification engineers to help customers optimize Arm-based SoC designs.

OneSpin Solutions is contributing the Scalable Infrastructure for Edge Computing (Scale4Edge) project. Funded under the ZuSE program run by Germany’s BMBF, the program is working to develop an ecosystem for edge processing. OneSpin will be focused on verifying functional correctness, functional safety, and security in RISC-V processors for use in commercial artificial intelligence and industry 4.0 designs.

Samsung Foundry used Synopsys’ 3DIC Compiler tool to design, implement and tape out a complex 5nm SoC featuring eight high-bandwidth memories (HBMs) in a single package. Samsung cited increased design productivity and a reduction in turnaround time from months to hours.

EOS and Ansys are collaborating to provide a streamlined workflow for developing additive manufacturing (AM) parts. In joining the EOS Developer Network, Ansys will enhance user AM processes via Ansys simulations and expedite printing by sending jobs directly to EOS’ 3D printing systems.

Numbers & Legal
Cadence reported third quarter financial results for 2020 with revenue of $667 million, up 15% from the same quarter last year. On a GAAP basis, earnings per share were $0.58 for Q3 2020, up 61.1% from $0.36 in Q3 2019. Non-GAAP earnings were $0.70 per share for the quarter, up 29.6% from $0.54 per share in the same quarter last year. “We are raising our 2020 revenue and earnings guidance primarily due to higher second half hardware and IP sales activity in China and continuing progress in our System Design and Analysis business,” said John Wall, senior vice president and CFO.

The legal battle between Nokia and Lenovo continued this month, according to Reuters. Last month, a Munich court ruled that Lenovo infringed on one of Nokia’s patents. Lenovo argued that Nokia “violated its own legal obligations by refusing to license its technology on Fair Reasonable and Non-Discriminatory (FRAND) terms to either Lenovo or our third-party suppliers whose parts include H.264 technology,” but the court rejected that assessment and ordered an injunction and a recall of products from retailers in Germany. Lenovo has appealed the ruling, but Nokia is now seeking enforcement of the injunction. Six other cases are ongoing in Germany, as well as cases in the United States, Brazil, and India.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

DVCon Europe takes place Oct. 27-28 as a virtual conference with tutorials, papers, posters, and panel sessions. Keynotes will cover topics including hardware DevOps, borrowing from software, automotive computing, and heterogenous design verification.

The Linley Fall Processor conference continues Oct. 27-29 with a keynote on TinyML and sessions on AI at the edge, heterogenous computing, SoC design, and in-memory compute.

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